Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, May 2013 — 07-Elec-A5 Electronics. Three hours, closed book; one approved Casio or Sharp calculator permitted. Six questions are printed, each worth 20 marks, and five constitute a complete paper — all six are solved below as a study resource. Op-amps are ideal with ±15 V supplies unless stated otherwise.
Reference texts. A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (Oxford): Ch. 5–7 (MOSFET and BJT amplifiers, common-emitter and common-gate stages), Ch. 4 (diode limiters, clamps and rectifiers), Ch. 13–14 (CMOS/NMOS inverter VTC and noise margins), and Ch. 2 (op-amp precision rectifiers and slew rate).
Given. Five inverting op-amp circuits with a $\pm10$ V sinusoidal input $v_{IN}$, ideal diodes (0.7 V drop), ideal op-amps rail-limited to $\pm15$ V.
Find. The output waveform of each circuit over one input cycle, with all break levels marked.
Approach. For each circuit hold the inverting input at virtual ground while a diode conducts, find the diode state versus input polarity, and note where the loop opens (op-amp saturates) or the output clips at a rail.
(a) Diode limiter in a T-network. With the diode off, the feedback is $5+5=10\ \text{k}\Omega$ and the gain is $-2$; the mid-node sits at $v_M=-v_{IN}$. For $v_{IN}\gt-0.7$ V the diode is reverse-biased and $v_{OUT}=-2v_{IN}$ (clipping at $-15$ V once $v_{IN}\gt7.5$ V). For $v_{IN}\lt-0.7$ V the diode clamps $v_M$ at $+0.7$ V, the feedback loop opens, and the op-amp saturates to $+15$ V.
(a) Output v_OUT(t). Dashed grey = input sine (10 V). For v_IN>-0.7 V, v_OUT=-2 v_IN (clips at -15 V for v_IN>7.5 V); for v_IN<-0.7 V the loop opens and the output saturates at +15 V.
(b) Dead-zone rectifier with unequal gains. The two anti-parallel diode+resistor legs select the input resistor by polarity. For $|v_{IN}|\lt0.7$ V both diodes are off and $v_{OUT}=0$ (dead zone). For $v_{IN}\gt0.7$ V the 2 kΩ leg conducts: $v_{OUT}=-\tfrac{5}{2}(v_{IN}-0.7)$ (clip $-15$ V at $v_{IN}=6.7$ V). For $v_{IN}\lt-0.7$ V the 1 kΩ leg conducts: $v_{OUT}=-5(v_{IN}+0.7)$ (clip $+15$ V at $v_{IN}=-3.7$ V).
(b) Output v_OUT(t). Dead zone |v_IN|<0.7 V gives 0 V; v_IN>0.7 V gives gain -2.5 (clip -15 V); v_IN<-0.7 V gives gain -5 (clip +15 V).
(c) Rectifier with a $+10$ V pull-up. The feedback diode conducts only for $v_{IN}\gt0$; then node $C$ sits at $-0.7$ V and a node equation with the $+10$ V/$3\ \text{k}\Omega$ pull-up gives $v_{OUT}=-v_{IN}-4.27\ \text{V}$ (so $-4.27$ V at $v_{IN}=0^{+}$ down to $-14.3$ V at $v_{IN}=10$ V). For $v_{IN}\lt0$ the diode blocks, the loop opens and the output saturates at $+15$ V.
(c) Output v_OUT(t). For v_IN>0, v_OUT = -v_IN - 4.27 V (biased by the +10 V pull-up); for v_IN<0 the diode blocks, the loop opens and the output saturates at +15 V.
(d) Dual-slope precision rectifier. The two anti-parallel feedback legs give a different gain each half. For $v_{IN}\gt0$ the 5 kΩ leg conducts: $v_{OUT}=-0.7-5v_{IN}$ (clip $-15$ V near $v_{IN}=2.9$ V). For $v_{IN}\lt0$ the 3 kΩ leg conducts: $v_{OUT}=+0.7-3v_{IN}$ (clip $+15$ V near $v_{IN}=-4.8$ V). The output is a rectified, sign-inverted input with slope $5$ on the positive half and $3$ on the negative half.
(d) Output v_OUT(t): dual-slope precision rectifier. Positive input -> gain -5 (clip -15 V); negative input -> gain -3, i.e. +3 v_IN (clip +15 V).
(e) Battery in the feedback. The ideal 3 V cell across the feedback resistor pins the output: with the virtual ground at 0 V and the cell $+$ terminal at the summing node, $v_{OUT}=0-3=-3\ \text{V}$, a constant, independent of the input. The 3 kΩ simply carries the offset current and does not affect $v_{OUT}$.
(e) Output v_OUT(t): the ideal 3 V cell in the feedback fixes v_OUT = -3 V, independent of the input.
Q3 — transfer summary
Circuit
Behaviour
(a)
vOUT=−2vIN for vIN>−0.7 V (clip −15 V); +15 V for vIN<−0.7 V
(b)
0 for |vIN|<0.7 V; −2.5(vIN−0.7) (+half); −5(vIN+0.7) (−half)
(c)
−vIN−4.27 V for vIN>0; +15 V (saturated) for vIN<0
(d)
−0.7−5vIN (+half); +0.7−3vIN (−half); rails at ±15 V