Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — May 2014 · 07-Elec-A5, Electronics. Closed-book; non-communicating calculator permitted; 3 hours. Five questions, 20 marks each; op-amps ideal with ±15 V supplies unless stated. All five are solved below.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 7th/8th ed. (diodes & wave-shaping Ch. 4; MOS amplifiers Ch. 7; BJT amplifiers Ch. 6–7; op-amp imperfections Ch. 2); R. C. Jaeger & T. N. Blalock, Microelectronic Circuit Design.
Check / reading of the figure. The problem text names a p-channel device while the schematic draws an n-channel symbol with its source at ground and the drain resistor labelled \(R_S\). The amplifier is a single common-source stage and its gain, output resistance and swing have the same magnitudes either way; it is solved here as a grounded-source common-source amplifier with drain resistor \(R_D=R_S=2\ \text{k}\Omega\) and load \(R_L=2\ \text{k}\Omega\). \(V_T\approx 25\ \text{mV}\) is not needed — MOS bias uses the square law.
Given. A grounded-source common-source amplifier biased by the divider \(R_1,R_2\) with drain resistor \(R_D=2\ \text{k}\Omega\) and a.c.-coupled load \(R_L=2\ \text{k}\Omega\); the device data and target operating point are tabulated below.
Q2 - Common-source stage: R1/R2 set the gate bias, RS is the drain resistor to VDD, output taken from the drain via C2 into RL.
Approach. Use the square-law to find the gate overdrive and bias point, split the gate divider using \(R_{in}=R_1\parallel R_2\), then get \(r_o\) for \(R_o\) and use the a.c. load line for the maximum swing.
Gate overdrive and gate voltage (part a). In saturation \(I_D=K\,V_{ov}^{2}\) (neglecting the small \(\lambda\) term for bias): $$V_{ov}=\sqrt{\frac{I_D}{K}}=\sqrt{\frac{2\ \text{mA}}{2\ \text{mA/V}^2}}=1\ \text{V},\qquad V_{GS}=|V_{TH}|+V_{ov}=2\ \text{V}.$$ With the source grounded the gate sits at \(V_G=2\ \text{V}\).
Solve the bias divider. \(V_G=V_{DD}\dfrac{R_2}{R_1+R_2}=2\ \text{V}\Rightarrow R_1=4R_2\); and the input resistance \(R_{in}=R_1\parallel R_2=100\ \text{k}\Omega\). Substituting \(R_1=4R_2\): \(\dfrac{4R_2^2}{5R_2}=0.8R_2=100\ \text{k}\Omega\), so $$\boxed{R_2=125\ \text{k}\Omega,\qquad R_1=500\ \text{k}\Omega.}$$ Check: \(V_D=V_{DD}-I_DR_D=10-(2\,\text{mA})(2\,\text{k}\Omega)=6\ \text{V}\), and \(V_{DS}=6\ \text{V}\gt V_{ov}=1\ \text{V}\) — saturation confirmed.
Output resistance (part b). The channel-length modulation gives \(r_o=\dfrac{1}{\lambda I_D}=\dfrac{1}{(0.01)(2\,\text{mA})}=50\ \text{k}\Omega\). Looking into the drain output node, \(R_o=R_D\parallel r_o\): $$R_o=\frac{(2\,\text{k}\Omega)(50\,\text{k}\Omega)}{52\,\text{k}\Omega}=\boxed{1.92\ \text{k}\Omega}.$$
Maximum undistorted swing (part c). For the a.c. signal the drain sees \(R_{ac}=R_D\parallel R_L=2\parallel2=1\ \text{k}\Omega\) (with \(r_o=50\,\text{k}\Omega\) negligible). From the quiescent point \(V_{D}=6\ \text{V},\ I_D=2\ \text{mA}\) the drain voltage may fall until the device leaves saturation at \(V_{DS}=V_{ov}=1\ \text{V}\) — a downward room of \(6-1=5\ \text{V}\); it may rise until the device cuts off, a room of \(I_D R_{ac}=(2\,\text{mA})(1\,\text{k}\Omega)=2\ \text{V}\). The smaller limit governs the symmetric swing: $$\hat v_o=\min(5,2)=2\ \text{V}\;\Rightarrow\;v_{o,\,pp}=\boxed{4\ \text{V}}.$$
