Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — December 2018 · 16-Elec-A5, Electronics. Closed-book, 3 hours. Answer all FIVE (5) questions; each worth 20 marks. Unless otherwise stated, op-amps are ideal and supply rails are ±15 V; ground and chassis are common.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (Oxford) — Ch. 4 (diode circuits & rectifiers), Ch. 5–7 (MOSFET and BJT amplifiers, biasing and small-signal models), Ch. 13–14 (CMOS/enhancement-load inverters), Ch. 2 (ideal op-amps, offset and feedback). Cross-reference: R. C. Jaeger & T. N. Blalock, Microelectronic Circuit Design.
Given. A single NMOS in the common-gate configuration: the gate is set by the $R_1$–$R_2$ divider and held at AC ground, the source is fed by the input through $C_1$ and biased by the ideal current source $I_{bias}$, and the drain drives $R_D$ with the output taken through $C_2$.
Given data — Question 3
Quantity
Value
Quantity
Value
$V_{TH}$
1 V
$V_{DD}$
10 V
$K$
1 mA/V$^2$
$I_{bias}$
2 mA
$\lambda$
0.1 V$^{-1}$
$R_D$
2 kΩ
$R_1,R_2$ (gate bias)
10 kΩ, 5 kΩ
$C_1,C_2$
$\infty$
Find. the small-signal voltage gain $A_v=v_o/v_{in}$, the input resistance $R_{in}$ looking into the source, and the output resistance $R_o$ looking into the drain.
[Figure not reproduced: Q3: common-gate NMOS stage — gate divider $R_1$/$R_2$ (AC-grounded), source driven through $C_1$ with $I_{bias}$, drain load $R_D$, output through $C_2$. See the official exam paper or the cited reference text.]
Q3: common-gate NMOS stage — gate divider $R_1$/$R_2$ (AC-grounded), source driven through $C_1$ with $I_{bias}$, drain load $R_D$, output through $C_2$.
Approach. Fix the bias point from $I_{bias}$ to get $g_m$ and $r_o$ (neglecting $\lambda$ for the DC solution, as usual), then apply the common-gate small-signal results.
Bias point. The current source sets $I_D=I_{bias}=2\text{ mA}$. From the saturation law (dropping $\lambda$ for bias), $I_D=\tfrac12 K V_{OV}^2$, so $$V_{OV}=\sqrt{\frac{2I_D}{K}}=\sqrt{\frac{2(2)}{1}}=2\text{ V}.$$
Voltage gain (a). A common-gate stage is non-inverting; including $r_o$, $$A_v=\frac{v_o}{v_{in}}=(1+g_m r_o)\frac{R_D}{R_D+r_o}=(1+10)\frac{2}{2+5}=\frac{22}{7}=\boxed{+3.14\text{ V/V}}.$$
Input resistance (b). Looking into the source (the ideal $I_{bias}$ adds no loading), $$R_{in}=\frac{R_D+r_o}{1+g_m r_o}=\frac{2+5}{11}\text{ k}\Omega=\boxed{636\ \Omega}\ \left(\approx 1/g_m\right).$$
Output resistance (c). Setting the input to zero grounds the source through $C_1$, so looking into the drain the transistor presents $r_o$ in parallel with $R_D$: $$R_o=R_D\,\|\,r_o=\frac{2\times5}{2+5}\text{ k}\Omega=\boxed{1.43\text{ k}\Omega}.$$