Question 4 of 5: Enhancement-Load NMOS Inverter (VTC)
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — December 2018 · 16-Elec-A5, Electronics. Closed-book, 3 hours. Answer all FIVE (5) questions; each worth 20 marks. Unless otherwise stated, op-amps are ideal and supply rails are ±15 V; ground and chassis are common.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (Oxford) — Ch. 4 (diode circuits & rectifiers), Ch. 5–7 (MOSFET and BJT amplifiers, biasing and small-signal models), Ch. 13–14 (CMOS/enhancement-load inverters), Ch. 2 (ideal op-amps, offset and feedback). Cross-reference: R. C. Jaeger & T. N. Blalock, Microelectronic Circuit Design.
Given. A driver NMOS $M_1$ (input on its gate, source grounded) and an identical load NMOS $M_2$ whose gate and drain are tied to $V_{DD}$. No numeric $V_{DD}$ or $V_t$ are supplied, so the levels are expressed symbolically; an illustrative plot uses $V_{DD}=5\text{ V}$, $V_t=1\text{ V}$.
Find. the VTC with $V_{OH}$, $V_{OL}$, $V_{IL}$, $V_{IH}$, the noise margins, and the operating region of each device.
[Figure not reproduced: Q4: enhancement-load inverter — load $M_2$ has gate and drain tied to $V_{DD}$; driver $M_1$ has its gate at $v_{IN}$ and source grounded. See the official exam paper or the cited reference text.]
Q4: enhancement-load inverter — load $M_2$ has gate and drain tied to $V_{DD}$; driver $M_1$ has its gate at $v_{IN}$ and source grounded.
Approach. The load $M_2$ (gate tied to its own drain toward $V_{DD}$) is always saturated when on and turns off one threshold below the rail. Sweep $v_{IN}$ and match the driver and load currents region by region.
Output high (c). For $v_{IN}\lt V_t$ the driver $M_1$ is cut off; the load carries no current, so its $V_{GS2}=V_t$ and the output rises only to $$V_{OH}=V_{DD}-V_t\quad(=4\text{ V for the illustrative values}).$$ This one-threshold loss is the hallmark of the enhancement load.
Slope $-1$ region and input thresholds (d). Just above $v_{IN}=V_t$ both transistors are saturated; for identical devices $\tfrac12K(v_{IN}-V_t)^2=\tfrac12K(V_{DD}-v_{OUT}-V_t)^2$ gives $$v_{OUT}=V_{DD}-v_{IN}\quad(\text{slope}=-1).$$ Its end-points are the unity-gain points $$V_{IL}=V_t\ (=1\text{ V}),\qquad V_{IH}=\frac{V_{DD}+V_t}{2}\ (=3\text{ V}),$$ where $M_1$ passes from saturation into triode ($v_{OUT}=v_{IN}-V_t=(V_{DD}-V_t)/2$).
Output low (c). At the maximum input $v_{IN}=V_{OH}$ the driver is deep in triode while the load stays saturated; equating the two currents yields $$v_{OUT}^2-(2V_{DD}-3V_t)\,v_{OUT}+\tfrac12(V_{DD}-V_t)^2=0\;\Rightarrow\;V_{OL}=\boxed{\tfrac{7-\sqrt{17}}{2}=1.44\text{ V}}\ (\text{illustrative}).$$ $V_{OL}$ does not reach 0 V — a second drawback of this load.
Noise margins (b). $$NM_H=V_{OH}-V_{IH}=\frac{V_{DD}-3V_t}{2}\ (=1\text{ V}),\qquad NM_L=V_{IL}-V_{OL}\ (=1-1.44=-0.44\text{ V}).$$ The negative $NM_L$ is the classic limitation of the enhancement-load inverter.
Regions and device modes (e). Region I ($v_{IN}\lt V_t$): $M_1$ cut-off, $M_2$ saturated ($v_{OUT}=V_{OH}$). Region II ($V_t\lt v_{IN}\lt V_{IH}$): $M_1$ and $M_2$ both saturated (the slope $-1$ transition). Region III ($v_{IN}\gt V_{IH}$): $M_1$ triode, $M_2$ saturated ($v_{OUT}\to V_{OL}$).
VTC (illustrative $V_{DD}=5$, $V_t=1$): flat at $V_{OH}=V_{DD}-V_t$, a slope $-1$ transition between $V_{IL}=V_t$ and $V_{IH}=(V_{DD}+V_t)/2$, settling to $V_{OL}$.
Check: the paper gives no numeric $V_{DD}$ or $V_t$, so the boxed numbers use the illustrative $V_{DD}=5\text{ V}$, $V_t=1\text{ V}$; the symbolic expressions ($V_{OH}=V_{DD}-V_t$, $V_{IL}=V_t$, $V_{IH}=(V_{DD}+V_t)/2$) are the graded results.
Results — Question 4 (symbolic; illustrative in parentheses)
