Question 2 of 5

Question 2

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. An n-channel MOSFET common-source stage with the square-law model $I_D=\tfrac12 K(V_{GS}-V_{TH})^2$ (in saturation, $\lambda=0$), gate biased by divider R_G1/R_G2, source degeneration R_S, drain load R_D, and an ac-coupled load R_L.

Find. (a) the four bias resistors; (b) the overall small-signal gain from the source v₁ to v_out. (Note: the printed “v_i/v_out” is the reciprocal of the usual voltage-gain definition and is taken here as v_out/v_i, with the reciprocal reported alongside.)

Approach. Fix the source and drain resistors from the required DC drops, get V_GS from the square law, and set the gate divider from V_G and the specified input resistance; then compute g_m and apply the degenerated CS gain, finally scaling by the input attenuation of R₁ with R_in.

1. (a) Source and drain resistors from the DC drops. $$R_S = \frac{V_S}{I_D} = \frac{3.5}{0.5\ \text{mA}} = \boxed{7\ \text{k}\Omega}, \qquad R_D = \frac{V_{DD}-V_D}{I_D} = \frac{15-6}{0.5\ \text{mA}} = \boxed{18\ \text{k}\Omega}.$$
2. Gate–source voltage from the square law. With $\lambda=0$ and $I_D=\tfrac12 K(V_{GS}-V_{TH})^2$, $$V_{GS}-V_{TH}=\sqrt{\frac{2I_D}{K}}=\sqrt{\frac{2(0.5\ \text{mA})}{4\ \text{mA/V}^2}}=0.5\ \text{V}\ \Rightarrow\ V_{GS}=1.5\ \text{V}.$$
3. Gate DC voltage. The gate sits above the source by V_GS: $$V_G = V_{GS} + V_S = 1.5 + 3.5 = 5\ \text{V}.$$
4. Gate divider. The divider must set $V_G$ and present $R_{in}=R_{G1}\|R_{G2}$: $$\frac{R_{G2}}{R_{G1}+R_{G2}}=\frac{V_G}{V_{DD}}=\frac{5}{15}=\frac13 \Rightarrow R_{G1}=2R_{G2},\qquad R_{G1}\|R_{G2}=\tfrac23 R_{G2}=1.67\ \text{M}\Omega.$$ Hence $R_{G2}=\boxed{2.5\ \text{M}\Omega}$ and $R_{G1}=\boxed{5.0\ \text{M}\Omega}$ (check: $5\|2.5=1.67\ \text{M}\Omega$, $V_G=15\cdot\tfrac{2.5}{7.5}=5\ \text{V}$).
5. (b) Transconductance. $$g_m = K(V_{GS}-V_{TH}) = \sqrt{2KI_D} = 4\ \text{mA/V}^2 \times 0.5\ \text{V} = 2\ \text{mA/V}.$$
6. AC drain load. R_D and R_L appear in parallel for the signal (V_DD is an ac ground, R_L is coupled through C₂): $$R_D\|R_L = 18\|200 = 16.5\ \text{k}\Omega.$$
7. Degenerated stage gain. With R_S un-bypassed and $r_o=\infty$ ($\lambda=0$), $$\frac{v_d}{v_g}=-\frac{g_m(R_D\|R_L)}{1+g_mR_S}=-\frac{(2\ \text{mA/V})(16.5\ \text{k}\Omega)}{1+(2\ \text{mA/V})(7\ \text{k}\Omega)}=-\frac{33.0}{15}=-2.20.$$
8. Input attenuation and overall gain. The gate sees R₁ feeding R_in: $$\frac{v_g}{v_i}=\frac{R_{in}}{R_1+R_{in}}=\frac{1.67}{0.10+1.67}=0.944,$$ $$\frac{v_{out}}{v_i}= 0.944\times(-2.20)=\boxed{-2.08}\quad\Bigl(\text{so } \tfrac{v_i}{v_{out}}\approx-0.48\Bigr).$$