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22-Elec-A5 Electronics · December 2019

Question 4 of 5

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams — December 2019, 16-Elec-A5 Electronics. Closed book; a Casio or Sharp approved calculator permitted. Three hours. Answer all five (5) questions; each worth 20 marks. Unless stated, op-amps are ideal with ±15 V supplies, and ground and chassis are common.

Reference texts. A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (Oxford, 2020) — diode piecewise-linear models & limiters (Ch. 4), MOSFET biasing & the common-source amplifier (Ch. 7), op-amp dynamics/slew rate (Ch. 2), CMOS inverter VTC and noise margins (Ch. 13), and precision/limiting op-amp–diode circuits (Ch. 4 & 18). B. Razavi, Fundamentals of Microelectronics, 2nd ed., is an equivalent secondary reference.

Question 4

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A complementary CMOS inverter: PMOS M2 (source at +VDD, threshold −|VTp|) over NMOS M1 (source at ground, threshold VTn), gates tied to vIN, drains tied to vOUT. Both devices obey the square law; transconductance parameters kn, kp.

Find. The VTC with all levels labelled; the output levels VOH/VOL; the input thresholds VIL/VIH (slope = −1 points); the noise margins; and the operating mode of each transistor in every region.

v_IN (V)v_OUT (V)V_ILV_IHV_MV_OHV_OLABCDECMOS inverter VTC (shown for V_DD=5, V_Tn=|V_Tp|=1)
CMOS inverter VTC with the five regions A–E. Illustrated for the symmetric case (VDD = 5 V, VTn = |VTp| = 1 V, kn = kp), for which VM = 2.5 V, VIL = 2.125 V, VIH = 2.875 V. Red dots mark the slope = −1 points.

Output levels (c). Because one transistor is always fully off at the extremes and the on device carries no static current, there is no resistive drop, so the output reaches the rails exactly:

$$\boxed{V_{OH}=V_{DD}}\qquad\boxed{V_{OL}=0}.$$

Regions and modes (a, e). Sweeping vIN from 0 to VDD:

  1. Region A — $v_{IN}<V_{Tn}$. NMOS cut-off, PMOS triode (deep). Output pinned at $v_{OUT}=V_{OH}=V_{DD}$.
  2. Region B — $V_{Tn}<v_{IN}<V_{IL}\ldots V_M$. NMOS saturation, PMOS triode. Output high but beginning to fall.
  3. Region C — near $V_M$. Both transistors in saturation; the VTC is steep (ideally vertical). The switching threshold is $$V_M=\frac{V_{Tn}+r\,(V_{DD}-|V_{Tp}|)}{1+r},\qquad r=\sqrt{\tfrac{k_p}{k_n}}.$$ For a matched inverter ($k_n=k_p$, $V_{Tn}=|V_{Tp}|$) this reduces to $V_M=V_{DD}/2$.
  4. Region D — $V_M\ldots V_{IH}<v_{IN}<V_{DD}-|V_{Tp}|$. NMOS triode, PMOS saturation. Output low, still falling.
  5. Region E — $v_{IN}>V_{DD}-|V_{Tp}|$. PMOS cut-off, NMOS triode (deep). Output pinned at $v_{OUT}=V_{OL}=0$.

Input thresholds (d). VIL and VIH are the two points where the VTC slope equals −1 (boundaries of the transition). For the matched inverter the standard results are

$$V_{IL}=\tfrac18\!\left(3V_{DD}+2V_{Tn}\right),\qquad V_{IH}=\tfrac18\!\left(5V_{DD}-2V_{Tn}\right),$$

i.e. symmetric about $V_M=V_{DD}/2$. With $V_{DD}=5$ V and $V_{Tn}=1$ V these give $V_{IL}=2.125$ V and $V_{IH}=2.875$ V.

Noise margins (b). By definition

$$\text{NM}_L=V_{IL}-V_{OL}=\tfrac18(3V_{DD}+2V_{Tn}),\qquad \text{NM}_H=V_{OH}-V_{IH}=\tfrac18(3V_{DD}+2V_{Tn}).$$

The matched inverter therefore has equal noise margins, $\text{NM}_L=\text{NM}_H=\tfrac18(3V_{DD}+2V_{Tn})=2.125$ V in the illustrated case — the largest achievable, which is why symmetry ($k_n=k_p$, $V_{Tn}=|V_{Tp}|$, $V_M=V_{DD}/2$) is the design goal.

Q4 — results (symmetric case shown numerically for VDD=5 V, Vt=1 V)
LevelExpressionValue
VOH / VOLVDD / 05 V / 0 V
VMVDD/2 (matched)2.5 V
VIL(3VDD+2VTn)/82.125 V
VIH(5VDD−2VTn)/82.875 V
NML = NMH(3VDD+2VTn)/82.125 V