Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, December 2014 —
07-Elec-B5, Advanced Electronics. Three hours; closed book; any
non-communicating calculator permitted. Answer all FIVE (5)
questions, each worth 20 marks. The paper instructs candidates to
state clearly any assumptions made where a question admits more than one
interpretation, to start each question on a new page, and to assume that
ground and chassis are common and that op amps are ideal.
Reference texts.
A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed.
— the principal reference for this subject (Ch. 4 zener regulators,
Ch. 8 cascodes, Ch. 10 frequency response, Ch. 11 feedback, Ch. 17 tuned
amplifiers).
B. Razavi, Fundamentals of Microelectronics, 2nd ed. — cited
by name in Question 4 of this paper (Example 9.9, p. 405).
P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and
Design of Analog Integrated Circuits, 5th ed. — for the differential
and feedback material.
All five questions on this paper are calculation questions built on a
circuit schematic, so each is worked in the standard
Given → Find → Figure → Approach → Steps →
Results shape. Every schematic below was redrawn from the printed figure; where the printed drawing decides an answer, the reading taken is
stated explicitly in a callout.
Find. The nominal regulated output voltage, the peak-to-peak
ripple that survives at the output when the raw supply carries 1 V p-p, and the
power efficiency of the regulator delivering that output into 4 Ω.
Figure 1.1 — Series regulator: zener reference D1 biased through R1, ideal op amp A1 as error amplifier, Darlington pass pair Q1–Q2, output returned directly to the inverting input.
Approach. Fix the zener operating point first (it is not
simply the rated 6.7 V until the bias current is checked), read the output
straight off the unity-gain feedback loop, treat the ripple as a small-signal
divider between $R_1$ and the zener's incremental resistance, and finish with a
power balance that counts every current drawn from $V_{DD}$ — collector,
base and reference alike.
Part (a) — locate the zener's actual operating point.
The op-amp input draws no current, so the whole of the current through $R_1$
flows in the diode, and the diode's own model must agree with it:
$$I_Z=\frac{V_{DD}-V_Z}{R_1},\qquad V_Z=V_{Z0}+r_z\,(I_Z-I_{Z0}).$$
Substituting the first into the second and solving the single linear equation,
$$V_Z=\frac{V_{Z0}-r_z I_{Z0}+r_z V_{DD}/R_1}{1+r_z/R_1}
=\frac{6.7-0.01+0.03030}{1.003030}=6.700\ \text{V},$$
whence $I_Z=(10-6.700)/3300=1.000$ mA. The design lands exactly on the
rated test point, which is why the incremental term vanishes — a
deliberate choice by the examiner and a useful check that the reading of the
circuit is right.
Read the output from the feedback connection. The output
node is wired straight back to the inverting input, so the loop is a unity-gain
follower around the reference. An ideal op amp forces
$v_-=v_+$, and here $v_+=V_Z$ and $v_-=V_{OUT}$:
$$\boxed{V_{OUT}=V_Z=6.70\ \text{V}}$$
There is no feedback divider in this circuit, so the output is the reference
itself; the Darlington pair contributes only current gain, and its two
$V_{BE}$ drops are absorbed by the op amp's output swing rather than appearing
at the load.
Part (b) — reduce the ripple problem to a divider.
For small perturbations the diode is just its incremental resistance $r_z$,
and $R_1$ feeds it from the rippling supply. Because the op-amp input draws no
signal current either, the reference node sees a plain resistive divider:
$$\Delta v_Z=\Delta v_{DD}\,\frac{r_z}{R_1+r_z}
=1.0\times\frac{10}{3300+10}=3.02\times10^{-3}\ \text{V}.$$
Carry that ripple through the loop to the output. With
infinite loop gain the error voltage is driven to zero, so whatever appears on
the reference appears on the output and nothing else does — the ripple
that couples through the pass transistors is suppressed by the loop:
$$\boxed{\Delta V_{OUT}\approx 3.02\ \text{mV peak-to-peak}}$$
Expressed as line rejection this is
$20\log_{10}(1/3.02\times10^{-3})=50.4$ dB. Notice that the answer is set
entirely by the reference, not by the pass device: improving this
regulator means a lower rz or a bigger $R_1$ (or a current
source in place of $R_1$), not a better transistor.
Part (c) — account for every current the supply must
deliver. The load takes
$$I_L=\frac{V_{OUT}}{R_L}=\frac{6.70}{4}=1.675\ \text{A},$$
which is the emitter current of $Q_2$. Working back up the Darlington,
$$I_{B2}=\frac{I_{E2}}{\beta+1}=\frac{1.675}{101}=16.58\ \text{mA},\qquad
I_{C2}=I_{E2}-I_{B2}=1.6584\ \text{A},$$
and since $I_{E1}=I_{B2}$,
$$I_{B1}=\frac{16.58\ \text{mA}}{101}=0.164\ \text{mA},\qquad
I_{C1}=16.42\ \text{mA}.$$
As a check on the bookkeeping, $I_{C1}+I_{C2}+I_{B1}=1.675$ A, which is exactly
the emitter current leaving the pair.
Form the power balance and the efficiency. Both collectors
and the op-amp output stage (which sources $I_{B1}$) are fed from $V_{DD}$, and
so is the reference string:
$$I_{DD}=I_{C1}+I_{C2}+I_{B1}+I_Z=1.675+0.001=1.676\ \text{A}.$$
$$P_{in}=V_{DD}I_{DD}=10\times1.676=16.76\ \text{W},$$
$$P_{L}=V_{OUT}I_L=6.70\times1.675=11.22\ \text{W},$$
$$\boxed{\eta=\frac{P_L}{P_{in}}=\frac{11.22}{16.76}=0.670\;\;\text{i.e.}\;\;67.0\ \%}$$
Sanity-check the number against the physics. A series
regulator can never beat the ratio of the voltages it stands between, and here
$V_{OUT}/V_{DD}=67.00$ percent. The computed 66.96 percent sits just below that
ceiling, the small shortfall being the 1 mA reference current and the base
currents; the missing 5.5 W is dissipated in the pass pair. This is the standing
argument for a switching regulator whenever the drop is large.
Check: the op amp's own quiescent supply current is not
specified, so it is neglected; only the base current it delivers to $Q_1$ is
counted. The stated $V_A=100$ V and $V_T=25$ mV do not enter any of the three
answers because the op amp is taken as ideal — they would be needed only
to evaluate the loop gain of a finite-gain error amplifier, and are included in
the question as part of a complete device description.