Feedback Amplifier — Input and Output Resistance: 22-Elec-B5 Advanced Electronics, December 2014, Q5

Question 5: Feedback Amplifier — Input and Output Resistance (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single n-channel MOSFET $M_1$ in saturation, biased by an ideal tail current source $I_{BIAS}$ returning to $-V_{DD}$. The signal $v_{IN}$ drives the source terminal; the drain carries the load resistor $R_D$ to $+V_{DD}$ and is the output node $v_{OUT}$; the divider $R_1$–$R_2$ runs from $v_{OUT}$ to ground with its tap connected to the gate. The answer is to be expressed in $g_m$, $R_D$, $R_1$ and $R_2$ only, so channel-length modulation and body effect are neglected ($r_o\to\infty$, $g_{mb}=0$).

Find. $R_{IN}$ (looking into the source node from the input generator) and $R_{OUT}$ (looking back into the drain node), first with the feedback network disabled and then with $R_1$ and $R_2$ finite.

Figure 5.1 — The stage is a common-gate forward path: v_IN enters at the source, and the divider R₁–R₂ samples v_OUT and returns a fraction of it to the gate.

Approach. Read the topology first: the forward amplifier is a common-gate stage, and the divider samples the output voltage and returns it to the gate, where it subtracts from the input in the gate–source loop. That is voltage-series (series–shunt) feedback, so $R_{IN}$ should rise and $R_{OUT}$ should fall. Both are obtained by test-source analysis on the three-node small-signal network.

Part (a) — reduce the circuit with the loop disabled. Setting $R_1=\infty$ disconnects the divider from the output, and $R_2=0$ ties the gate directly to ground. What remains is a plain common-gate stage: signal in at the source, out at the drain, gate at ac ground, and the tail current source an ac open.
Input resistance with no feedback. Driving the source with a test voltage $v_x$ makes $v_{gs}=-v_x$, so the transistor draws $i_x=-g_mv_{gs}=g_mv_x$ out of the test source. Therefore $$\boxed{R_{IN}=\frac{1}{g_m}}$$ the familiar low input resistance that makes a common-gate stage a current buffer rather than a voltage amplifier.
Output resistance with no feedback. Nulling the input source grounds the source terminal, so $v_{gs}=0$ and the controlled source is dead; with $r_o$ neglected the transistor branch is an open circuit, and the only element left at the drain node is the load resistor: $$\boxed{R_{OUT}=R_D}$$
Part (b) — describe the loop before analysing it. The gate draws no current, so the divider is unloaded and simply reports a fraction of the output to the gate, $$v_G=\beta\,v_{OUT},\qquad \beta=\frac{R_2}{R_1+R_2},$$ while the same divider hangs $R_F=R_1+R_2$ across the output node as a load. Since the gate–source voltage is $v_G-v_S=\beta v_{OUT}-v_{IN}$, the fed-back signal subtracts from the input in series with it, which is the defining feature of series mixing.
Solve the drain node for the output. Applying a test voltage $v_x$ at the source and writing KCL at the drain, with the drain current $g_mv_{gs}$ leaving that node, $$\frac{v_{OUT}}{R_D}+\frac{v_{OUT}}{R_F}+g_m\big(\beta v_{OUT}-v_x\big)=0,$$ $$v_{OUT}=\frac{g_m v_x}{G_D+g_m\beta},\qquad G_D=\frac{1}{R_D}+\frac{1}{R_F}.$$
Solve the source node for the input resistance. The transistor injects its channel current into the source node, so $i_x=g_m(v_x-\beta v_{OUT})$. Substituting the previous result, $v_x-\beta v_{OUT}=v_x\,G_D/(G_D+g_m\beta)$, and therefore $$R_{IN}=\frac{v_x}{i_x}=\frac{1}{g_m}+\frac{\beta}{G_D} =\frac{1}{g_m}+\beta\big(R_D\,\|\,R_F\big),$$ which in the four requested symbols is $$\boxed{R_{IN}=\frac{1}{g_m}+\frac{R_2R_D}{R_D+R_1+R_2}}$$
Solve for the output resistance. Nulling the input generator grounds the source, so $v_{gs}=v_G=\beta v_y$ for a test voltage $v_y$ at the drain. KCL there gives $i_y=v_y/R_D+v_y/R_F+g_m\beta v_y$, hence $$R_{OUT}=R_D\,\Big\|\,\big(R_1+R_2\big)\,\Big\|\,\frac{R_1+R_2}{g_mR_2} =\cfrac{1}{\cfrac{1}{R_D}+\cfrac{1}{R_1+R_2}+\cfrac{g_mR_2}{R_1+R_2}}$$ $$\boxed{R_{OUT}=\frac{R_1+R_2}{\dfrac{R_1+R_2}{R_D}+1+g_mR_2}}$$ The three parallel terms are, in order, the load itself, the divider loading the output, and the feedback proper — only the last carries $g_m$, and it is the one that does the regulating.
Check the limits and the direction of the effect. Letting $R_1\to\infty$ and $R_2\to0$ sends $\beta\to0$ and $R_F\to\infty$, recovering $R_{IN}=1/g_m$ and $R_{OUT}=R_D$ exactly as in part (a). For a worked illustration take $g_m=2$ mA/V, $R_D=10$ kΩ, $R_1=50$ kΩ and $R_2=5$ kΩ: then $\beta=1/11$, and $R_{IN}$ rises from 500 Ω to 1269 Ω while $R_{OUT}$ falls from 10 kΩ to 3.33 kΩ. Both move in the direction voltage-series feedback predicts — series mixing raises the input resistance, voltage sampling lowers the output resistance — which is the qualitative check to run before trusting either algebraic result.

Check: the topology of the schematic decides the whole answer. The input generator drives the source of $M_1$ (the tail node shared with $I_{BIAS}$), and the gate is connected only to the $R_1$–$R_2$ tap — this is a common-gate forward path, not the common-source stage a hurried reading suggests. Had the input entered at the gate, $R_{IN}$ would be infinite and the eight marks of part (a) unearnable, which is itself confirmation of the reading taken. Channel-length modulation and body effect are neglected throughout, as the instruction to express the answer in $g_m$, $R_D$, $R_1$ and $R_2$ alone requires.

Final results.

Part	Quantity	Result
(a)	$R_{IN}$, no feedback	$1/g_m$
(a)	$R_{OUT}$, no feedback	$R_D$
(b)	Feedback factor	$\beta=R_2/(R_1+R_2)$
(b)	$R_{IN}$, finite $R_1$, $R_2$	$\dfrac{1}{g_m}+\dfrac{R_2R_D}{R_D+R_1+R_2}$
(b)	$R_{OUT}$, finite $R_1$, $R_2$	$R_D\,\\|\,(R_1+R_2)\,\\|\,\dfrac{R_1+R_2}{g_mR_2}$
—	Illustration ($g_m=2$ mA/V, $R_D=10$ kΩ, $R_1=50$ kΩ, $R_2=5$ kΩ)	$R_{IN}: 500\to1269$ Ω; $R_{OUT}: 10\to3.33$ kΩ

Topic. Voltage-series (series–shunt) feedback applied to a common-gate stage; the effect of feedback on terminal resistances.

Key relations. Common-gate $R_{IN}=1/g_m$ and $R_{OUT}=R_D$ (with $r_o\to\infty$); feedback factor $\beta=R_2/(R_1+R_2)$; series mixing multiplies input resistance by $(1+A\beta)$; voltage sampling divides output resistance by $(1+A\beta)$; resistance seen at a node with a controlled source is found by test-source analysis, not by inspection.

Why this works. Feedback changes a terminal resistance by changing how hard the circuit fights the test source. At the input, a positive test voltage at the source drives the drain positive (a common-gate stage is non-inverting), the divider lifts the gate, and the higher gate voltage partially cancels the $v_{gs}$ that the test source created — less $v_{gs}$ means less current for the same test voltage, so the resistance goes up. At the output the argument runs the other way: a positive test voltage at the drain lifts the gate, increases $v_{gs}$, and pulls extra current out of the test source, so the resistance goes down. The two effects are the same loop seen from its two ends, which is why the same $\beta$ appears in both answers.

Common pitfall. Mistaking the topology and answering $R_{IN}=\infty$ because a MOSFET gate draws no current — here the gate is not the input. A second error is treating the divider as ideal: $R_1+R_2$ loads the output node in parallel with $R_D$, and dropping that term overstates $R_{OUT}$ and understates the loop's loading, particularly when $R_1+R_2$ is comparable with $R_D$.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §11.3–11.5 (the four feedback topologies and their effect on input and output resistance) and §7.3.4 (common-gate stage); Gray, Hurst, Lewis & Meyer, 5th ed., Ch. 8.

Question 5 of 5: Feedback Amplifier — Input and Output Resistance

Question 5: Feedback Amplifier — Input and Output Resistance (20 marks)