Paper format: National Exams, May 2014 — 07-Elec-B5 Advanced Electronics. Three hours, CLOSED BOOK, any non-communicating calculator permitted. Answer all FIVE (5) questions; all questions are worth 20 marks each. Op-amps are ideal and supply voltages are ±15 V unless stated otherwise; in schematics ground and chassis are common. Candidates are urged to state any assumption made in interpreting a question.
Reference texts (22-Elec-B5 Advanced Electronics):
- A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. — Ch. 7 (Transistor Amplifiers), Ch. 8 (Differential and Multistage Amplifiers), Ch. 10 (Frequency Response & Tuned Amplifiers), Ch. 11 (Feedback), Ch. 12 (Output Stages and Power Amplifiers).
- B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. — Ch. 3 (Single-Stage Amplifiers), Ch. 4 (Differential Amplifiers), Ch. 9 (Cascodes and Frequency Response).
- P. R. Gray, P. J. Hurst, S. H. Lewis & R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. — Ch. 3–4 (single-transistor and differential stages), Ch. 8 (Feedback).
Check — two engineering assumptions used throughout this paper.
- Bias currents are taken from the printed current sources, not from the drawn resistors. Questions 1, 3 and 4 all show an ideal current source setting the branch current, so each transistor's quiescent current is read directly off that source. Where a drawn resistor would imply a different current (Question 4's 1 kΩ emitter resistor), the paper's stated 1 mA governs and the resistor is treated as part of an undrawn bias network — see the Question 4 note.
- Channel-length modulation is used in the small-signal model but not in the bias calculation. The tail (or bias) source fixes $I_D$ exactly, so $V_{OV}=\sqrt{2I_D/K}$ and $g_m=KV_{OV}=\sqrt{2KI_D}$ are computed with $\lambda$ set aside, while $r_o=1/(\lambda I_D)$ is carried into every gain expression. This is the standard convention and the error it introduces is well under one percent.
