22-Elec-B5 Advanced Electronics · May 2014

Question 5 of 5: Class-B Push-Pull Output Stage — Power, Device Dissipation and Efficiency

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format: National Exams, May 2014 — 07-Elec-B5 Advanced Electronics. Three hours, CLOSED BOOK, any non-communicating calculator permitted. Answer all FIVE (5) questions; all questions are worth 20 marks each. Op-amps are ideal and supply voltages are ±15 V unless stated otherwise; in schematics ground and chassis are common. Candidates are urged to state any assumption made in interpreting a question.

Reference texts (22-Elec-B5 Advanced Electronics):

A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. — Ch. 7 (Transistor Amplifiers), Ch. 8 (Differential and Multistage Amplifiers), Ch. 10 (Frequency Response & Tuned Amplifiers), Ch. 11 (Feedback), Ch. 12 (Output Stages and Power Amplifiers).
B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. — Ch. 3 (Single-Stage Amplifiers), Ch. 4 (Differential Amplifiers), Ch. 9 (Cascodes and Frequency Response).
P. R. Gray, P. J. Hurst, S. H. Lewis & R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. — Ch. 3–4 (single-transistor and differential stages), Ch. 8 (Feedback).

Check — two engineering assumptions used throughout this paper.

Bias currents are taken from the printed current sources, not from the drawn resistors. Questions 1, 3 and 4 all show an ideal current source setting the branch current, so each transistor's quiescent current is read directly off that source. Where a drawn resistor would imply a different current (Question 4's 1 kΩ emitter resistor), the paper's stated 1 mA governs and the resistor is treated as part of an undrawn bias network — see the Question 4 note.
Channel-length modulation is used in the small-signal model but not in the bias calculation. The tail (or bias) source fixes $I_D$ exactly, so $V_{OV}=\sqrt{2I_D/K}$ and $g_m=KV_{OV}=\sqrt{2KI_D}$ are computed with $\lambda$ set aside, while $r_o=1/(\lambda I_D)$ is carried into every gain expression. This is the standard convention and the error it introduces is well under one percent.

Question 5: Class-B Push-Pull Output Stage — Power, Device Dissipation and Efficiency (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A complementary emitter-follower output stage: NPN $Q_1$ collector to $+V_{CC}$, PNP $Q_2$ collector to $-V_{EE}$, emitters joined at $v_{out}$ with $R_L$ to ground. Diodes $D_1$, $D_2$ biased by $I_1$ and $I_2$ set the quiescent point, and the question directs that each transistor conducts negligibly around $v_{IN}=0$ — i.e. treat the stage as class B, each device conducting for its own half cycle. $V_{CC} = |V_{EE}| = 10$ V, $R_L = 8\ \Omega$, sinusoidal drive, base currents and bias-source power neglected.

Find. The maximum power delivered to the load; the maximum power dissipated in one output transistor and the drive level at which it occurs; and the maximum conversion efficiency.

Figure 5.1 — Question 5 circuit: complementary class-B pair, $Q_1$ conducting the positive half cycle into $R_L$ and $Q_2$ the negative half, with $D_1$/$D_2$ and $I_1$/$I_2$ providing the (negligible) quiescent bias.

Approach. Work in terms of the output amplitude $V_p$: the load power is a simple sinusoidal rms result, the supply power follows from the half-wave-rectified average current each rail delivers, and the difference — shared equally by the two transistors — is maximised by calculus, not by inspection.

Part (a) — Write the load power and maximise it. For a sinusoidal output of amplitude $V_p$ across $R_L$, the rms voltage is $V_p/\sqrt{2}$, so $$P_L = \frac{\left(V_p/\sqrt{2}\right)^2}{R_L} = \frac{V_p^2}{2R_L}.$$ The emitter followers can swing the output to within a saturation voltage of each rail; taking the ideal limit $V_{p,\max}=V_{CC}=10$ V as the question's data allow, $$\boxed{P_{L,\max} = \frac{V_{CC}^2}{2R_L} = \frac{(10\ \text{V})^2}{2(8\ \Omega)} = 6.25\ \text{W}}$$ A real pair with $V_{CE,\text{sat}} \approx 0.3$ V would deliver $(9.7)^2/16 = 5.88$ W, about 6 percent less.
Part (b) — Find the average current each rail supplies. $Q_1$ conducts only the positive half cycle, so the current it draws from $+V_{CC}$ is a half-wave-rectified sinusoid of peak $V_p/R_L$, whose average over a full period is $$I_{CC,\text{avg}} = \frac{1}{2\pi}\int_0^{\pi}\frac{V_p}{R_L}\sin\theta\ d\theta = \frac{V_p}{\pi R_L}.$$ Each rail therefore supplies $P_{CC} = V_{CC}V_p/(\pi R_L)$, and the two together supply $P_S = 2V_{CC}V_p/(\pi R_L)$.
Express the dissipation of one transistor. $Q_1$ dissipates whatever its rail supplies minus the half of the load power it produces: $$P_{Q1}(V_p) = \frac{V_{CC}V_p}{\pi R_L} - \frac{V_p^2}{4R_L}.$$ This is a downward parabola in $V_p$, so — and this is the point of the ten marks — the worst case is not at full drive.
Maximise the dissipation. Differentiating and setting the derivative to zero, $$\frac{dP_{Q1}}{dV_p} = \frac{V_{CC}}{\pi R_L} - \frac{V_p}{2R_L} = 0 \;\Longrightarrow\; V_p = \frac{2V_{CC}}{\pi} = \frac{2(10)}{\pi} = 6.37\ \text{V}.$$ Substituting that amplitude back, $$\boxed{P_{Q1,\max} = \frac{V_{CC}^2}{\pi^2R_L} = \frac{(10\ \text{V})^2}{\pi^2(8\ \Omega)} = 1.27\ \text{W} \quad \text{at}\ V_p = 6.37\ \text{V}}$$ At that drive the load receives $V_p^2/2R_L = 2.53$ W while the pair burns $2\times1.27 = 2.53$ W — the classic class-B result that peak device stress occurs at 64 percent of full output, where the stage is only half efficient.
Part (c) — Form the efficiency and evaluate it at full drive. $$\eta = \frac{P_L}{P_S} = \frac{V_p^2/(2R_L)}{2V_{CC}V_p/(\pi R_L)} = \frac{\pi}{4}\cdot\frac{V_p}{V_{CC}},$$ which rises linearly with drive and peaks when $V_p = V_{CC}$: $$\boxed{\eta_{\max} = \frac{\pi}{4} = 0.785 \;\Rightarrow\; 78.5\ \text{percent}}$$ At that point the supplies deliver $P_S = 2(10)(10)/(\pi\cdot 8) = 7.96$ W, the load takes 6.25 W, and the two transistors share the remaining 1.71 W (0.854 W each) — well below the 1.27 W worst case found in part (b), which is why the heat-sink must be sized from part (b) and never from part (c).
Sanity-check the three answers against each other. The numbers must be mutually consistent: $\eta_{\max} = P_{L,\max}/P_{S,\max} = 6.25/7.96 = 0.785$, matching $\pi/4$ exactly; and the ratio $P_{Q1,\max}/P_{L,\max} = (V_{CC}^2/\pi^2R_L)\big/(V_{CC}^2/2R_L) = 2/\pi^2 = 0.203$, a fixed fraction independent of supply and load. Any class-B stage dissipates at most about a fifth of its rated output power per device.

Figure 5.2 — Load power and single-transistor dissipation versus output amplitude for $V_{CC}=10$ V, $R_L = 8\ \Omega$. $P_L$ grows as $V_p^2$ all the way to 6.25 W at full swing, while $P_{Q1}$ turns over at $V_p = 2V_{CC}/\pi$ and is falling by the time the stage reaches full output.

Part	Quantity	Result
(a)	Maximum load power $P_{L,\max}=V_{CC}^2/2R_L$	6.25 W (5.88 W allowing 0.3 V saturation)
(b)	Drive at which device dissipation peaks	$V_p = 2V_{CC}/\pi = $ 6.37 V
(b)	Maximum dissipation in $Q_1$, $V_{CC}^2/\pi^2R_L$	1.27 W (2.53 W for the pair)
(c)	Supply power at full drive	7.96 W
(c)	Maximum efficiency $\pi/4$	78.5 percent
(c)	Dissipation per device at full drive	0.854 W (less than the part (b) worst case)

Topic: Class-B complementary output stage — load power, worst-case device dissipation, and the $\pi/4$ efficiency ceiling.

Key relations: $P_L = V_p^2/(2R_L)$; supply current per rail $= V_p/(\pi R_L)$; $P_S = 2V_{CC}V_p/(\pi R_L)$; per-device dissipation $P_Q = V_{CC}V_p/(\pi R_L)-V_p^2/(4R_L)$, maximised at $V_p = 2V_{CC}/\pi$ giving $P_{Q,\max}=V_{CC}^2/(\pi^2R_L)$; efficiency $\eta = (\pi/4)(V_p/V_{CC})$, maximum $\pi/4 = 78.5$ percent.

Why this works: Everything follows from one observation: in class B each device conducts for exactly half the cycle, so the current it draws from its rail is a half-wave rectified sine and its average is $1/\pi$ of the peak, not $1/2$. The load, by contrast, receives a full sine and its power goes as the square of the amplitude. Supply power is therefore linear in $V_p$ while load power is quadratic — and the difference between a line and an upward parabola is a downward parabola, which is precisely why the transistors run hottest at partial drive. Class A has no such subtlety (its supply current is constant and its worst case is at zero signal), which is why candidates trained on class A instinctively evaluate part (b) at full swing and lose the marks. The $\pi/4$ ceiling is the same ratio in disguise: at full swing the load takes $V_{CC}^2/2R_L$ while the rails give up $2V_{CC}^2/\pi R_L$, and the quotient is $\pi/4$ with every circuit parameter cancelling.

Common pitfall: Evaluating $P_{Q1}$ at $V_p = V_{CC}$ instead of differentiating — that gives 0.854 W, one third low, and would under-size a heat sink by the same factor. A second is halving the wrong thing: $P_{Q1}$ is the dissipation of one transistor and already accounts for its single half-cycle of conduction, so it must not be halved again. A third is including the bias network: the question explicitly says to neglect $I_1$ and $I_2$, and doing so is what makes $\pi/4$ exact rather than an upper bound.

Source: Sedra & Smith, Microelectronic Circuits, 8th ed., Ch. 12 §12.3–12.4 (class-B output stage: power dissipation, efficiency, and the class-AB biasing that these diodes provide); Gray, Hurst, Lewis & Meyer, 5th ed., Ch. 5.

← Question 4 Back to the paper →