22-Elec-B5 Advanced Electronics · May 2014

Question 1 of 5: MOSFET Differential Pair — Design, Common-Mode Behaviour and Loaded Waveforms

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Question 1: MOSFET Differential Pair — Design, Common-Mode Behaviour and Loaded Waveforms (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

The input is applied differentially and symmetrically: $+v_{IN}/2$ on the gate of $M_1$ and $-v_{IN}/2$ on the gate of $M_2$. The output is taken single-ended from the drain of $M_2$ (node $v_{D2}$) through $C_O$.

Find. The load resistors $R_1$ and $R_2$ that give an unloaded single-ended gain of exactly 5 V/V; the common-mode input resistance; the common-mode input range; and the two output waveforms with a 5 kΩ load hung on the output node.

[Figure not reproduced: Figure 1.1 — Question 1 circuit as printed: matched pair $M_1$, $M_2$ with drain loads $R_1$, $R_2$, an ideal tail source $I_{BIAS}$, and the signal taken from $v_{D2}$ through $C_O$ into $R_L$. See the official exam paper.]

Approach. Fix the quiescent point from the tail current, get $g_m$ and $r_o$ per device, size $R_2$ from the single-ended differential gain $A_d = \tfrac{1}{2}g_m(R_2\|r_o)$, then use the same bias point for the saturation limits that bound the common-mode range and for the a.c. load that sets the loaded swing.

1. Part (a) — Establish the quiescent point from the tail source. The tail divides equally between the matched devices, so each carries $$I_D = \frac{I_{BIAS}}{2} = \frac{1\ \text{mA}}{2} = 0.5\ \text{mA}.$$ Inverting the saturation law $I_D = \tfrac{1}{2}K V_{OV}^2$ gives the overdrive $$V_{OV} = \sqrt{\frac{2I_D}{K}} = \sqrt{\frac{2(0.5\ \text{mA})}{1\ \text{mA/V}^2}} = 1.00\ \text{V}, \qquad V_{GS} = V_{TH} + V_{OV} = 2.00\ \text{V}.$$
2. Small-signal parameters follow directly. Differentiating the saturation law, $g_m = K V_{OV} = \sqrt{2KI_D}$, and the channel-length term supplies the output resistance: $$g_m = (1\ \text{mA/V}^2)(1.00\ \text{V}) = 1.00\ \text{mA/V}, \qquad r_o = \frac{1}{\lambda I_D} = \frac{1}{(0.02)(0.5\ \text{mA})} = 100\ \text{k}\Omega.$$
3. Write the single-ended differential gain. With $\pm v_{IN}/2$ on the two gates, $v_{gs2} = -v_{IN}/2$, so the signal current in $M_2$ is $i_{d2} = -g_m v_{IN}/2$ and the drain voltage rises: $$\frac{v_{D2}}{v_{IN}} = +\tfrac{1}{2}\,g_m\,(R_2 \,\|\, r_o).$$ The output is non-inverting because the signal is taken from the drain of the device driven by the negative half of the input.
4. Solve for the required drain resistance. Setting the open-circuit gain to 5 V/V (with $C_O=\infty$ and $R_L$ removed, $v_{OUT}=v_{D2}$): $$R_2\,\|\,r_o = \frac{2 \times 5}{g_m} = \frac{10}{1\ \text{mA/V}} = 10.0\ \text{k}\Omega,$$ and removing the shunting effect of the 100 kΩ $r_o$ leaves $$R_2 = \left(\frac{1}{10\ \text{k}\Omega} - \frac{1}{100\ \text{k}\Omega}\right)^{-1} = 11.11\ \text{k}\Omega.$$ Matching the two sides keeps the pair balanced (equal quiescent drain voltages, and therefore the best common-mode rejection and the widest symmetric swing), so $$\boxed{R_1 = R_2 = 11.1\ \text{k}\Omega}$$ Had $r_o$ been ignored the design would have returned $10.0\ \text{k}\Omega$ — an 11 percent error in the resistor and a gain of only 4.5 V/V once the real $r_o$ is present, so the $\lambda$ given in the question is doing real work here.
5. Record the quiescent drain voltages. Each load carries the 0.5 mA half-tail: $$V_{D1} = V_{D2} = V_{DD} - I_D R = 10 - (0.5\ \text{mA})(11.11\ \text{k}\Omega) = 4.44\ \text{V}.$$ This number is needed twice more, in parts (c) and (d).
6. Part (b) — Evaluate the common-mode input resistance. Drive both gates together with $v_{icm}$ and measure the current that flows in. The gate of a MOSFET is the plate of a capacitor separated from the channel by the gate oxide; at d.c. no conduction path exists, so the current drawn is zero regardless of the tail resistance, the load resistors or the common-mode level: $$\boxed{R_{icm} = \frac{v_{icm}}{i_{icm}} \to \infty}$$ In a real device the finite value is set by gate-oxide leakage and is of order $10^{12}$–$10^{15}\ \Omega$ — large enough that it never appears in a design equation. The result is worth contrasting with the bipolar differential pair, where base current flows and $R_{icm} = 2\left[r_\pi + (\beta+1)R_{EE}\right]$ is finite and often the limiting specification. What does limit this circuit is not resistance but capacitance: at signal frequencies the common-mode input impedance is that of $C_{gs}+C_{gd}$ per gate, which at 1 kHz (part (d)) is still tens of megohms and remains negligible.
7. Part (c) — Upper end of the common-mode input range. Raising both gates together does not change the drain currents — the tail source holds them — so $V_{D}$ stays pinned at 4.44 V while $V_G$ rises. The pair fails when $M_1$ and $M_2$ leave saturation, i.e. when $v_{DS} = V_{OV}$, equivalently $V_G \le V_D + V_{TH}$: $$V_{ICM,\max} = V_D + V_{TH} = 4.44 + 1.00 = 5.44\ \text{V}.$$
8. Lower end of the common-mode input range. Lowering both gates pushes the common source node down with them, since $V_S = V_{ICM} - V_{GS} = V_{ICM} - 2.00\ \text{V}$. The floor is whatever compliance voltage the tail source needs above $-V_{EE}$. Two readings must be reported because the source is drawn as an ideal symbol:
   • Ideal tail source (zero compliance, as drawn): $V_{ICM,\min} = -V_{EE} + V_{GS} = -10 + 2.00 = -8.00\ \text{V}$.
   • Tail realised as one saturated NMOS carrying $I_{BIAS}$ with the same $K$: it needs $V_{OV,tail} = \sqrt{2I_{BIAS}/K} = \sqrt{2}=1.41\ \text{V}$, giving $V_{ICM,\min} = -10 + 1.41 + 2.00 = -6.59\ \text{V}$.
   The design answer, quoting the practical (transistor-tail) case and the ideal case as the outer bound, is $$\boxed{-6.59\ \text{V} \;\le\; V_{ICM} \;\le\; +5.44\ \text{V}\quad(\text{ideal tail: } -8.00\ \text{V}\ \text{lower limit})}$$ i.e. a usable window of 12.0 V, widening to 13.4 V if the tail source truly needs no headroom.
9. Part (d) — Find the a.c. load once $R_L$ is connected. $C_O$ is infinite, so at 1 kHz it is a short and $R_L$ appears directly across the drain of $M_2$ for signals while blocking the 4.44 V d.c. level from reaching the load. The a.c. resistance at that drain is $$R_{ac} = R_2 \,\|\, r_o \,\|\, R_L = 11.11\ \text{k}\Omega \,\|\, 100\ \text{k}\Omega \,\|\, 5\ \text{k}\Omega = 10\ \text{k}\Omega \,\|\, 5\ \text{k}\Omega = 3.33\ \text{k}\Omega.$$
10. Compute the loaded gain and the two swings. Substituting into the same gain expression, $$A_v = \tfrac{1}{2} g_m R_{ac} = \tfrac{1}{2}(1\ \text{mA/V})(3.33\ \text{k}\Omega) = 1.667\ \text{V/V},$$ so a 0.5 V peak-to-peak input (amplitude 0.25 V) produces an output amplitude of $1.667 \times 0.25 = 0.417\ \text{V}$, i.e. 0.833 V peak-to-peak. The two requested waveforms are therefore identical in shape, amplitude and phase and differ only in their d.c. level: $$\boxed{v_{D2}(t) = 4.44 + 0.417\sin(2\pi \cdot 10^3 t)\ \text{V}, \qquad v_{out}(t) = 0 + 0.417\sin(2\pi \cdot 10^3 t)\ \text{V}}$$ $v_{D2}$ swings between 4.03 V and 4.86 V about its 4.44 V bias; $v_{out}$ swings symmetrically about zero because $C_O$ blocks the d.c. and $R_L$ returns the load side to ground.
11. Confirm the sketch is legitimately a clean sine. Each gate sees only half the input, so $|v_{gs}| = 0.125\ \text{V}$ against $V_{OV} = 1\ \text{V}$; the small-signal ratio $|v_{gs}|/2V_{OV} = 0.0625$ is well inside the usual 0.1 linearity guideline, so second-harmonic distortion is small and the waveform is drawn as an undistorted sinusoid. Saturation also holds over the whole swing: the lowest drain excursion, 4.03 V, is far above the highest gate excursion less $V_{TH}$ ($0.125 - 1 = -0.875$ V), so neither device enters triode.