22-Elec-B5 Advanced Electronics · May 2014

Question 2 of 5: Common-Gate Stage with Series-Shunt Feedback — Input and Output Resistance

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format: National Exams, May 2014 — 07-Elec-B5 Advanced Electronics. Three hours, CLOSED BOOK, any non-communicating calculator permitted. Answer all FIVE (5) questions; all questions are worth 20 marks each. Op-amps are ideal and supply voltages are ±15 V unless stated otherwise; in schematics ground and chassis are common. Candidates are urged to state any assumption made in interpreting a question.

Reference texts (22-Elec-B5 Advanced Electronics):

A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. — Ch. 7 (Transistor Amplifiers), Ch. 8 (Differential and Multistage Amplifiers), Ch. 10 (Frequency Response & Tuned Amplifiers), Ch. 11 (Feedback), Ch. 12 (Output Stages and Power Amplifiers).
B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. — Ch. 3 (Single-Stage Amplifiers), Ch. 4 (Differential Amplifiers), Ch. 9 (Cascodes and Frequency Response).
P. R. Gray, P. J. Hurst, S. H. Lewis & R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. — Ch. 3–4 (single-transistor and differential stages), Ch. 8 (Feedback).

Check — two engineering assumptions used throughout this paper.

Bias currents are taken from the printed current sources, not from the drawn resistors. Questions 1, 3 and 4 all show an ideal current source setting the branch current, so each transistor's quiescent current is read directly off that source. Where a drawn resistor would imply a different current (Question 4's 1 kΩ emitter resistor), the paper's stated 1 mA governs and the resistor is treated as part of an undrawn bias network — see the Question 4 note.
Channel-length modulation is used in the small-signal model but not in the bias calculation. The tail (or bias) source fixes $I_D$ exactly, so $V_{OV}=\sqrt{2I_D/K}$ and $g_m=KV_{OV}=\sqrt{2KI_D}$ are computed with $\lambda$ set aside, while $r_o=1/(\lambda I_D)$ is carried into every gain expression. This is the standard convention and the error it introduces is well under one percent.

Question 2: Common-Gate Stage with Series-Shunt Feedback — Input and Output Resistance (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single NMOS device $M_1$ with drain load $R_D$ returned to $+V_{DD}$. The signal source $v_{IN}$ drives the source terminal; $R_{IN}$ is measured looking into that node. The drain is the output node $v_{OUT}$, and $R_{OUT}$ is measured looking back into it. A resistive divider $R_1$ (from $v_{OUT}$ down) in series with $R_2$ (to ground) has its tap connected to the gate. No $\lambda$ is quoted, so $r_o \to \infty$, and the answers are to be written in terms of $g_m$, $R_D$, $R_1$ and $R_2$ only.

Find. $R_{IN}$ and $R_{OUT}$ first with the feedback path removed ($R_1 = \infty$, $R_2 = 0$), then in closed form with $R_1$ and $R_2$ finite.

Figure 2.1 — Question 2 circuit. The divider samples $v_{OUT}$ in shunt and returns $\beta v_{OUT}$ to the gate, where it subtracts from $v_{IN}$ inside the gate-source loop — i.e. series mixing.

Approach. Identify the topology, then get both resistances from two node equations rather than from feedback bookkeeping: the gate is a pure high-impedance tap so $v_G = \beta v_{OUT}$ exactly, with $\beta = R_2/(R_1+R_2)$, and everything else follows from one KCL at the drain plus a test source at the port of interest.

Part (a) — Reduce the circuit with the feedback removed. Setting $R_1 = \infty$ opens the sampling path and $R_2 = 0$ ties the gate to ground, leaving a textbook common-gate stage: gate grounded, signal into the source, output at the drain. Looking into the source, a test voltage $v_x$ makes $v_{gs} = -v_x$, so the channel delivers $i_x = g_m v_x$ back into the test source and $$R_{IN}\big|_{\text{no fb}} = \frac{v_x}{g_m v_x} = \frac{1}{g_m}.$$
Output resistance without feedback. With $v_{IN}$ nulled the source node is held at ground, so $v_{gs} = 0$ and the dependent source is dead; because $r_o \to \infty$ the only element left between the drain and a.c. ground is the load resistor: $$\boxed{R_{IN} = \frac{1}{g_m}, \qquad R_{OUT} = R_D \qquad (R_1 \to \infty,\ R_2 = 0)}$$ For orientation the mid-band gain of this stage is $A_v = +g_m R_D$, non-inverting, which is the common-gate signature.
Part (b) — Fix the feedback factor. The gate draws no current, so the divider is unloaded and the tap voltage is an exact fraction of the output: $$v_G = \beta\, v_{OUT}, \qquad \beta = \frac{R_2}{R_1+R_2}.$$ The divider does, however, load the drain node with its series total $R_F = R_1 + R_2$, so define the total resistive load $$R_L' = R_D \,\|\, R_F = \frac{R_D(R_1+R_2)}{R_D+R_1+R_2}.$$
Write one KCL at the drain. Currents leaving the drain node through the load, through the divider, and into the channel must sum to zero. With $v_S$ the source-node (input) voltage and $v_{gs} = v_G - v_S$: $$\frac{v_{OUT}}{R_D} + \frac{v_{OUT}-v_G}{R_1} + g_m\left(v_G - v_S\right) = 0.$$ Substituting $v_G = \beta v_{OUT}$ and noting $(1-\beta)/R_1 = 1/R_F$, the divider branch collapses neatly: $$v_{OUT}\left[\frac{1}{R_D} + \frac{1}{R_F} + g_m\beta\right] = g_m v_S \;\Longrightarrow\; A_v = \frac{v_{OUT}}{v_S} = \frac{g_m R_L'}{1+g_m\beta R_L'}.$$ The quantity $T \equiv g_m \beta R_L'$ that appears in the denominator is the loop gain, and it is the single number the rest of the derivation turns on.
Input resistance with feedback. The only element at the source node is the channel itself, so the current drawn from the driving source is $i_S = g_m(v_S - v_G) = g_m(v_S - \beta A_v v_S)$. Using $1-\beta A_v = 1/(1+T)$, $$R_{IN} = \frac{v_S}{i_S} = \frac{1+T}{g_m} = \frac{1}{g_m} + \beta R_L'.$$ Writing $\beta R_L'$ out in the requested variables cancels the $(R_1+R_2)$ factors: $$\boxed{R_{IN} = \frac{1}{g_m} + \frac{R_D R_2}{R_D+R_1+R_2} \;=\; \frac{R_D+R_1+R_2+g_mR_DR_2}{g_m\left(R_D+R_1+R_2\right)}}$$ Feedback has raised the input resistance by the factor $(1+T)$ — the signature of series mixing, and the reason this stage can be driven by a source that a bare common-gate input would swamp.
Output resistance with feedback. Null the input source ($v_S = 0$) and drive the drain with a test voltage $v_x$; then $v_G = \beta v_x$ and $v_{gs} = \beta v_x$, so the channel current adds to the current the test source must supply: $$i_x = \frac{v_x}{R_D} + \frac{v_x}{R_F} + g_m\beta v_x \;\Longrightarrow\; R_{OUT} = \frac{R_L'}{1+T}.$$ In the requested variables, $$\boxed{R_{OUT} = \frac{R_D\left(R_1+R_2\right)}{R_D+R_1+R_2+g_mR_DR_2}}$$ Feedback has lowered the output resistance by the same factor $(1+T)$ — the signature of shunt (voltage) sampling. Both results collapse correctly to part (a): letting $R_1 \to \infty$ with $R_2 = 0$ sends $\beta \to 0$, $T \to 0$, $R_F \to \infty$, and returns $1/g_m$ and $R_D$.
Cross-check with a worked numerical case. Take $g_m = 2$ mA/V, $R_D = 5$ kΩ, $R_1 = 20$ kΩ, $R_2 = 5$ kΩ. Then $\beta = 0.2$, $R_F = 25$ kΩ, $R_L' = 4.167$ kΩ, and $T = 1.667$. The closed forms give $R_{IN} = 1.333$ kΩ (up from 500 Ω), $R_{OUT} = 1.563$ kΩ (down from 5 kΩ), and $A_v = g_mR_{OUT} = 3.125$ V/V (down from 10 V/V). Each resistance has moved by exactly $1+T = 2.667$, and the identity $A_v = g_m R_{OUT}$ — which falls straight out of the two boxed expressions — is a fast way to check the algebra in the exam room.

Part	Quantity	Result
(a)	$R_{IN}$, no feedback	$1/g_m$
(a)	$R_{OUT}$, no feedback	$R_D$
(b)	Feedback factor and loop gain	$\beta = R_2/(R_1+R_2)$; $T = g_m\beta\left(R_D\\|(R_1{+}R_2)\right)$
(b)	$R_{IN}$, with feedback	$\dfrac{1}{g_m}+\dfrac{R_DR_2}{R_D+R_1+R_2} = \dfrac{1+T}{g_m}$
(b)	$R_{OUT}$, with feedback	$\dfrac{R_D(R_1+R_2)}{R_D+R_1+R_2+g_mR_DR_2}$
(b)	Closed-loop gain (bonus check)	$A_v = g_mR_{OUT} = \dfrac{g_mR_L'}{1+T}$

Topic: Series-shunt (voltage-voltage) feedback around a common-gate stage — how mixing and sampling decide which port resistance rises and which falls.

Key relations: $\beta = R_2/(R_1+R_2)$; $R_L' = R_D\|(R_1+R_2)$; loop gain $T = g_m\beta R_L'$; $R_{IN}=(1+T)/g_m$; $R_{OUT}=R_L'/(1+T)$; $A_v = g_mR_L'/(1+T)$. Common-gate open-loop values: $R_{IN}=1/g_m$, $R_{OUT}=R_D$, $A_v=+g_mR_D$.

Why this works: Feedback topology is read off the two connections, not off the drawing style. The divider is connected across the output node, so it senses output voltage: that is shunt sampling, and shunt sampling always divides the output resistance by $(1+T)$ because the loop fights any change the test source tries to make. At the input, the fed-back signal arrives at the gate while the drive arrives at the source, so the two appear in series around the gate-source loop and subtract as voltages: that is series mixing, and series mixing always multiplies the input resistance by $(1+T)$ because the loop opposes the $v_{gs}$ the test source is trying to establish. Doing the algebra by direct nodal analysis rather than by the two-port feedback recipe avoids the usual trap of having to compute loading networks separately — here the drain loading by $R_F$ and the (zero) gate loading fall out automatically.

Common pitfall: The commonest error is reading the schematic as a common-source stage, because the gate is the terminal the divider touches and it looks like the input. It is not: the source arrow at the bottom-left is where $v_{IN}$ connects, and part (a)'s hint — grounding the gate by setting $R_2 = 0$ — only makes sense for a common-gate amplifier. The second pitfall is forgetting that the divider loads the drain, and quoting $R_{OUT}=R_D/(1+T)$ instead of $R_L'/(1+T)$; when $R_1+R_2$ is comparable with $R_D$ that is a large error.

Source: Sedra & Smith, Microelectronic Circuits, 8th ed., Ch. 11 §11.1–11.5 (general feedback structure, the four topologies, series-shunt analysis) and Ch. 7 §7.3.5 (common-gate stage); Gray, Hurst, Lewis & Meyer, 5th ed., Ch. 8.

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