Question 2 of 5: Common-emitter amplifier — mid-band gain and the two 3 dB frequencies
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, December 2015 — 07-Elec-B5
Advanced Electronics. Three hours, CLOSED BOOK; any non-communicating
calculator permitted. Answer all FIVE (5) questions; all questions
are worth 20 marks each. In schematics ground and chassis are common; op-amps are
ideal and supplies are ±15 V unless stated otherwise. Candidates are urged to
state any interpretation assumptions inside their answer — this solution does
so in the shaded Check callouts.
Reference texts.
A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. —
Ch. 4 (diodes / shunt and series regulators), Ch. 7 (transistor amplifiers),
Ch. 10 (frequency response, open-circuit time constants), Ch. 11 (feedback),
Ch. 12 (output stages), Ch. 17 (tuned amplifiers).
B. Razavi, Fundamentals of Microelectronics, 2nd ed. — Ch. 8
(bias and small-signal models), Ch. 11 (frequency response, Miller's theorem),
Ch. 12 (feedback topologies).
P. R. Gray, P. J. Hurst, S. H. Lewis & R. G. Meyer, Analysis and Design
of Analog Integrated Circuits, 5th ed. — Ch. 7 (frequency response),
Ch. 8 (feedback).
C. K. Alexander & M. N. O. Sadiku, Fundamentals of Electric Circuits,
7th ed. — Ch. 14 (resonance, bandwidth and quality factor).
Check — how the figures were recovered. Every circuit on this paper carries data that exists only in the drawing (which
branch a component sits in, which transistor terminal the source drives). Where a drawing
is ambiguous or under-specified, the reading used is stated explicitly in a
Check callout inside that question rather than being buried in the
arithmetic.
Question 2: Common-emitter amplifier — mid-band gain and the two 3 dB frequencies (20 marks)
Find. The mid-band voltage gain vOUT/vS, the lower
3 dB corner fL set by C1, the upper 3 dB corner fH, and the
second high-frequency pole.
Q2 — common-emitter stage. C2 = ∞ places the emitter at signal ground, so Ibias sets the operating point only; C1 couples the source to a base biased through R1.
Approach. Find the operating point from Ibias and get
gm and rπ; take the mid-band gain of the bypassed common-emitter
stage; put C1 against the resistance seen at the base for fL; and
split Cμ by Miller's theorem to obtain the two high-frequency poles.
Part (a) — Establish the bias point and the hybrid-π parameters.
The current source in the emitter fixes IE = Ibias = 1 mA, so
$$I_C=\alpha I_E=\frac{\beta}{\beta+1}I_E=\frac{100}{101}(1\ \text{mA})=0.990\ \text{mA}$$
$$g_m=\frac{I_C}{V_T}=\frac{0.990\ \text{mA}}{25\ \text{mV}}=39.6\ \text{mA/V},
\qquad r_\pi=\frac{\beta}{g_m}=\frac{100}{39.6\ \text{mA/V}}=2.53\ \text{k}\Omega$$
The DC base voltage is $-I_B R_1 \approx -10\ \text{mV}\approx 0$, so
$V_E\approx-0.7\ \text{V}$ and
$V_C=V_{CC}-I_C R_L=10-4.95=5.05\ \text{V}$: with
$V_{CE}=5.75\ \text{V}\gg V_{CE(sat)}$ the device is comfortably active.
Take the mid-band gain. In the mid-band C1 is a short and
C2 holds the emitter at signal ground, so the stage is a plain common emitter
whose base is driven directly by vS (the source is drawn ideal, and
R1 only shunts it). With ro neglected the load is RL alone:
$$\boxed{\frac{v_{OUT}}{v_S}=-g_m R_L=-(39.6\ \text{mA/V})(5\ \text{k}\Omega)=-198\ \text{V/V}}$$
i.e. about $-200$ V/V, or 45.9 dB with a 180° phase inversion.
Part (b) — Find the resistance that C1 works against.
Looking out from the coupling capacitor, the left-hand side is the ideal source
(zero ohms) and the right-hand side is the amplifier input:
$$R_{C1}=R_{sig}+\left(R_1\parallel r_\pi\right)=0+\frac{(1)(2.525)}{1+2.525}\ \text{k}\Omega=716\ \Omega$$
C2 is infinite and so contributes no low-frequency pole; C1 alone sets
the lower corner:
$$\boxed{f_L=\frac{1}{2\pi C_1 R_{C1}}=\frac{1}{2\pi(5\ \mu\text{F})(716\ \Omega)}=44.4\ \text{Hz}}$$
Part (c) — Split Cμ with Miller's theorem.
Cμ bridges base and collector across a gain of $-g_mR_L=-198$, so it appears
as two grounded capacitors:
$$C_{in}=C_\mu\left(1+g_mR_L\right)=2\ \text{pF}\,(199)=398\ \text{pF},\qquad
C_{out}=C_\mu\left(1+\frac{1}{g_mR_L}\right)=2.01\ \text{pF}$$
The huge input capacitance is the classic penalty of the inverting stage: a 2 pF
device capacitance behaves like 398 pF at the base.
Evaluate the dominant (input) pole. Cin sees the amplifier's
own input resistance $R_1\parallel r_\pi=716\ \Omega$, so
$$\boxed{f_H=\frac{1}{2\pi\left(R_1\parallel r_\pi\right)C_{in}}
=\frac{1}{2\pi(716\ \Omega)(398\ \text{pF})}=5.6\times10^{5}\ \text{Hz}=558\ \text{kHz}}$$
As a check, the exact single-capacitor result for the same driving resistance uses the
open-circuit time constant of Cμ,
$R_{\mu}=R_{sig}(1+g_mR_L)+R_L=716(199)+5000=148\ \text{k}\Omega$, giving
$1/(2\pi R_\mu C_\mu)=539\ \text{kHz}$ — within 3.5 % of the Miller estimate,
which confirms the input node is genuinely dominant.
Part (d) — Evaluate the second pole at the collector. The output
half of the Miller split works against RL:
$$\boxed{f_{p2}=\frac{1}{2\pi R_L C_{out}}=\frac{1}{2\pi(5\ \text{k}\Omega)(2.01\ \text{pF})}
=1.58\times10^{7}\ \text{Hz}=15.8\ \text{MHz}}$$
That is 28 times above fH, so the single-pole roll-off assumed in part (c) is
justified; beyond fp2 the response falls at 40 dB/decade. (The exact transfer
function also carries a right-half-plane zero at
$g_m/(2\pi C_\mu)=3.2\ \text{GHz}$, far outside the useful band.)
Q2 — straight-line magnitude response. The mid-band plateau of 45.9 dB (198 V/V) runs from fL = 44 Hz to fH = 558 kHz, with the second pole at 15.8 MHz steepening the roll-off to 40 dB/decade.
Part
Quantity
Result
—
Operating point
IC = 0.990 mA, gm = 39.6 mA/V, rπ = 2.53 kΩ
(a)
Mid-band gain vOUT/vS
−198 V/V (45.9 dB, inverting)
(b)
Lower 3 dB frequency fL
44.4 Hz
(c)
Upper 3 dB frequency fH
5.6 × 105 Hz (558 kHz; 539 kHz by exact time constant)
(d)
Second high-frequency pole fp2
1.58 × 107 Hz (15.8 MHz)
Check — the source resistance used in parts (c) and (d).
The schematic draws vS as an ideal voltage source with no series resistance, and
R1 as a shunt from the base node to ground (which is what gives the base its DC
path). Taken absolutely literally, the base node would then be driven from zero ohms, the
Miller input pole would recede to infinity, and the circuit would have a single pole at
$1/(2\pi R_L C_\mu)=15.9\ \text{MHz}$ — leaving part (d) with nothing to answer. The
reading used here, and the only one that makes both (c) and (d) earnable while using the
given R1, is that the base node is driven through the amplifier's own input
resistance $R_1\parallel r_\pi=716\ \Omega$. Part (a), which does not depend on that
resistance, is unaffected either way.