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22-Elec-B5 Advanced Electronics · December 2015

Question 3 of 5: Tuned amplifier with a gate tank — centre frequency, gain and bandwidth

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, December 2015 — 07-Elec-B5 Advanced Electronics. Three hours, CLOSED BOOK; any non-communicating calculator permitted. Answer all FIVE (5) questions; all questions are worth 20 marks each. In schematics ground and chassis are common; op-amps are ideal and supplies are ±15 V unless stated otherwise. Candidates are urged to state any interpretation assumptions inside their answer — this solution does so in the shaded Check callouts.

Reference texts.

Check — how the figures were recovered. Every circuit on this paper carries data that exists only in the drawing (which branch a component sits in, which transistor terminal the source drives). Where a drawing is ambiguous or under-specified, the reading used is stated explicitly in a Check callout inside that question rather than being buried in the arithmetic.

Question 3: Tuned amplifier with a gate tank — centre frequency, gain and bandwidth (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

QuantitySymbolValue
Transconductance parameterK1 mA/V2 (ID = ½KVOV2)
Threshold voltageVTH1 V
Channel-length modulationλ0 (ro = ∞)
Gate-source / gate-drain capacitanceCgs, Cgd10 pF, 1 pF
Tank inductor and capacitorL1, C11 μH, 200 pF
Source resistanceRS1 kΩ
Drain loadRL2 kΩ
Bias currentIbias2 mA
Source bypass capacitorC2∞

Find. The centre (resonant) frequency ωo of the tuned stage, the voltage gain vOUT/vS at that frequency, and the 3 dB bandwidth.

+−vsRSvINC1L1M1RL+VDDvOUTIbiasC2
Q3 — tuned common-source stage. The L1–C1 tank sits at the GATE, in parallel to ground, and is driven from vS through RS; the drain carries a plain resistive load RL.

Check — which node carries the tank. This matters: the drain is broadband and it is the gate node that is frequency-selective, so RS (not RL) sets the bandwidth. The device capacitances Cgs and Cgd are given precisely because they land in parallel with C1 and must be counted.

Approach. Bias the transistor to get gm, add the device capacitances (Cgd after Miller multiplication) to C1 to form the total tank capacitance, then use the standard parallel-RLC results: resonance where the susceptances cancel, gain set by the drain load once the tank is open, and bandwidth 1/(RC) with R the resistance loading the tank.

  1. Part (a) — Bias the transistor and get gm. With $I_D=\tfrac12 K V_{OV}^2$ and ID = Ibias = 2 mA, $$V_{OV}=\sqrt{\frac{2I_D}{K}}=\sqrt{\frac{2(2\ \text{mA})}{1\ \text{mA/V}^2}}=2.0\ \text{V}, \qquad V_{GS}=V_{TH}+V_{OV}=3.0\ \text{V}$$ $$g_m=KV_{OV}=\sqrt{2KI_D}=2.0\ \text{mA/V}$$ The drain sits at $V_D=V_{DD}-I_DR_L=10-4=6\ \text{V}$, well above $V_{OV}$, so M1 is saturated as assumed.
  2. Assemble the total tank capacitance. Cgs is already from gate to (AC-grounded) source, so it adds directly. Cgd bridges the gate and a drain that swings $-g_mR_L=-4$ times harder, so by Miller's theorem it appears at the gate as $$C_M=C_{gd}\left(1+g_mR_L\right)=1\ \text{pF}\,\bigl(1+(2\ \text{mA/V})(2\ \text{k}\Omega)\bigr)=5\ \text{pF}$$ $$C_{tot}=C_1+C_{gs}+C_M=200+10+5=215\ \text{pF}$$
  3. Resonate the tank. At resonance the inductive and capacitive susceptances cancel: $$\boxed{\omega_o=\frac{1}{\sqrt{L_1C_{tot}}} =\frac{1}{\sqrt{(1\ \mu\text{H})(215\ \text{pF})}}=6.82\times10^{7}\ \text{rad/s}}$$ which is $f_o=\omega_o/2\pi=10.85\ \text{MHz}$.
  4. Part (b) — Take the gain at resonance. At ωo the parallel L–C combination presents an infinite impedance, so no signal current flows in RS and the whole source voltage appears at the gate, $v_{gs}=v_S$. The drain then drives RL with ro = ∞: $$\boxed{\left.\frac{v_{OUT}}{v_S}\right|_{\omega_o}=-g_mR_L =-(2\ \text{mA/V})(2\ \text{k}\Omega)=-4.0\ \text{V/V}}$$ i.e. 12.0 dB with a 180° inversion. The drain node has its own pole at $1/[2\pi R_L C_{gd}(1+1/g_mR_L)]=63.7\ \text{MHz}$, six times above ωo, so it costs only 1.4 % of the magnitude and is neglected.
  5. Part (c) — Find the bandwidth from the tank's loading. Replace the source by its Norton equivalent, $i=v_S/R_S$ in parallel with RS: the gate node is then a parallel RLC with R = RS. For such a circuit the 3 dB bandwidth is independent of L and is fixed by the R–C product: $$\boxed{\text{BW}=\frac{1}{R_SC_{tot}}=\frac{1}{(1\ \text{k}\Omega)(215\ \text{pF})} =4.65\times10^{6}\ \text{rad/s}=740\ \text{kHz}}$$ The corresponding quality factor is $$Q=\frac{\omega_o}{\text{BW}}=\frac{6.82\times10^{7}}{4.65\times10^{6}}=14.7 =R_S\sqrt{\frac{C_{tot}}{L_1}}$$ the two expressions agreeing exactly, which is the cheap arithmetic check on this part.
−3 dB (0.707)ω1ω0ω2BW = ω2 − ω1|gain|angular frequency ω (rad/s)
Q3 — band-pass response of the gate tank (Q = 14.7). The gain peaks at −4.0 V/V at ωo = 6.82 × 107 rad/s and falls 3 dB at the edges of a 4.65 × 106 rad/s window.
PartQuantityResult
—Bias pointVOV = 2.0 V, VGS = 3.0 V, gm = 2.0 mA/V
—Total tank capacitanceCtot = 200 + 10 + 5 = 215 pF
(a)Centre frequency ωo6.82 × 107 rad/s (10.85 MHz)
(b)Gain at ωo−4.0 V/V (12.0 dB, inverting)
(c)3 dB bandwidth4.65 × 106 rad/s (740 kHz)
(c)Quality factorQ = 14.7

Check — counting the device capacitances. If Cgs and the Miller-multiplied Cgd are ignored and only C1 = 200 pF is resonated, the answer to (a) becomes $1/\sqrt{L_1C_1}=7.07\times10^{7}\ \text{rad/s}$ (11.25 MHz) and the bandwidth becomes $5.0\times10^{6}\ \text{rad/s}$ — each about 7 % away from the values above. The full count is used here because the paper supplies Cgs and Cgd and they sit in parallel with the tank; a candidate who quotes the C1-only figures should say so explicitly.