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22-Elec-B5 Advanced Electronics · December 2015

Question 4 of 5: Shunt–shunt feedback amplifier — input and output resistance

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, December 2015 — 07-Elec-B5 Advanced Electronics. Three hours, CLOSED BOOK; any non-communicating calculator permitted. Answer all FIVE (5) questions; all questions are worth 20 marks each. In schematics ground and chassis are common; op-amps are ideal and supplies are ±15 V unless stated otherwise. Candidates are urged to state any interpretation assumptions inside their answer — this solution does so in the shaded Check callouts.

Reference texts.

Check — how the figures were recovered. Every circuit on this paper carries data that exists only in the drawing (which branch a component sits in, which transistor terminal the source drives). Where a drawing is ambiguous or under-specified, the reading used is stated explicitly in a Check callout inside that question rather than being buried in the arithmetic.

Question 4: Shunt–shunt feedback amplifier — input and output resistance (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

QuantitySymbolValue
Drain loadRD3 kΩ
Gate shunt resistorR220 kΩ
Feedback resistorR1∞ in (a), 100 kΩ in (b)
Feedback coupling capacitorC1∞ (AC short, DC block)
Bias currentIbias1 mA
Transconductance parameterK1 mA/V2
Threshold voltageVTH1 V
Channel-length modulationλ0 (ro = ∞)

Find. RIN looking into the amplifier from vIN and ROUT looking back into the drain node, first with the feedback path removed and then with R1 = 100 kΩ closing the loop.

+−vINRINR2R1C1M1RD+VDDvOUTROUTIbias−VEE
Q4 — common-source stage with shunt–shunt (voltage-shunt) feedback: R1 in series with C1 returns the drain signal to the gate node, which is also shunted to ground by R2.

Approach. Bias M1 from Ibias to get gm; with R1 open the gate is purely resistive and the drain purely RD; with R1 in place, apply Miller's theorem to the feedback resistor (equivalently, solve the two node equations) to obtain the reduced input resistance, and kill vIN to obtain the output resistance.

  1. Part (a) — Bias the transistor. The tail current source fixes ID = Ibias = 1 mA, so with $I_D=\tfrac12KV_{OV}^2$, $$V_{OV}=\sqrt{\frac{2(1\ \text{mA})}{1\ \text{mA/V}^2}}=1.414\ \text{V},\qquad V_{GS}=V_{TH}+V_{OV}=2.41\ \text{V},\qquad g_m=\sqrt{2KI_D}=1.414\ \text{mA/V}$$ C1 blocks DC, so no current flows in R1 or R2 and the gate sits at 0 V; the source therefore rests at −2.41 V and the drain at $V_{DD}-I_DR_D=10-3=7\ \text{V}$, giving VDS = 9.41 V, comfortably saturated.
  2. Read off the open-loop resistances. With R1 = ∞ the only element between the input terminal and ground is R2, because a MOSFET gate draws no current: $$\boxed{R_{IN}=R_2=20\ \text{k}\Omega}$$ Looking back into the drain with vIN = 0 the gate is held at zero, so the controlled source is dormant and λ = 0 makes ro infinite: $$\boxed{R_{OUT}=R_D=3\ \text{k}\Omega}$$
  3. Part (b) — Find the gain that the feedback resistor sees. Writing KCL at the drain with the gate at vG and the source at signal ground, $$\frac{v_O-v_G}{R_1}+\frac{v_O}{R_D}+g_mv_G=0 \quad\Rightarrow\quad A_v=\frac{v_O}{v_G}=\frac{R_D\left(1-g_mR_1\right)}{R_1+R_D}$$ $$A_v=\frac{3\ \text{k}\Omega\left(1-(1.414\ \text{mA/V})(100\ \text{k}\Omega)\right)}{103\ \text{k}\Omega}=-4.09\ \text{V/V}$$ Note this is well below the −gmRD = −4.24 of the bare stage, and lower still because R1 now loads the drain.
  4. Miller the feedback resistor into the input. A resistor bridging a node pair with gain Av appears at the input as $R_1/(1-A_v)$; carrying the drain loading exactly gives the closed form $$R_f=\frac{R_1+R_D}{1+g_mR_D}=\frac{100+3}{1+(1.414)(3)}\ \text{k}\Omega =\frac{103}{5.243}\ \text{k}\Omega=19.65\ \text{k}\Omega$$ The feedback path has turned a 100 kΩ resistor into a 19.65 kΩ load on the input node — the signature of shunt feedback.
  5. Combine with R2 for the closed-loop input resistance. $$\boxed{R_{IN}=R_2\parallel R_f=\frac{(20)(19.65)}{20+19.65}\ \text{k}\Omega=9.91\ \text{k}\Omega}$$ a factor of 2.02 below the open-loop 20 kΩ, which is exactly the amount of shunt feedback applied at that node.
  6. Find the closed-loop output resistance. To measure ROUT the input source is set to zero; because vIN is an ideal voltage source connected directly to the gate node, that grounds the gate and disables the controlled source. The drain then sees only RD in parallel with the feedback network back to that grounded node: $$\boxed{R_{OUT}=R_D\parallel R_1=\frac{(3)(100)}{103}\ \text{k}\Omega=2.91\ \text{k}\Omega}$$ The 3 % reduction is simply R1 loading the drain; with an ideal voltage source driving the gate there is no loop left to reduce ROUT further, which is worth saying explicitly.
  7. Cross-check the whole result numerically. Solving the two-node conductance system directly (inject 1 A at the gate node, λ = 0, source at signal ground) returns $R_{IN}=9\,910.9\ \Omega$ and $A_v=-4.0899$, matching the closed forms above to five figures — the check that the Miller reduction was applied to the right node pair.
PartQuantityResult
—Bias pointID = 1 mA, VOV = 1.414 V, gm = 1.414 mA/V
(a)RIN, no feedback20 kΩ
(a)ROUT, no feedback3 kΩ
(b)Mid-band gain with R1 = 100 kΩ−4.09 V/V
(b)Feedback resistance seen at the gate19.65 kΩ
(b)RIN, feedback closed9.91 kΩ
(b)ROUT, feedback closed2.91 kΩ

Check — the source terminal of M1. The drawing terminates the source of M1 on the Ibias current source alone, with no bypass capacitor shown (unlike Questions 2, 3 and 5, where a C2 is drawn explicitly). Treated as a literally ideal current source it would be an AC open circuit, forcing id = 0 and making the loop gain zero — the “feedback amplifier” of the question stem would have no feedback at all. The reading used here is the standard one: the bias source is bypassed, so the source terminal is at signal ground. RIN and ROUT are evaluated at the two arrows drawn on the figure, i.e. RIN looking right from vIN into the R2/gate node and ROUT looking left into the drain node.