22-Elec-B5 Advanced Electronics · May 2015

Question 2 of 5: Common-Emitter Stage — Mid-Band Gain and Both 3 dB Frequencies

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2015 — 07-Elec-B5 Advanced Electronics. Three hours, CLOSED BOOK, any non-communicating calculator permitted. Five questions, 20 marks each; all five must be answered. The paper directs candidates to state any assumptions made, to treat ground and chassis as common, and to assume ideal op-amps on ±15 V rails unless a question says otherwise.

Reference texts. B. Razavi, Fundamentals of Microelectronics, 2nd ed. (Ch. 9, Cascode Stages and Current Mirrors — Question 1 cites Example 9.9 by name); A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (Ch. 8 Building Blocks of IC Amplifiers, Ch. 9 Differential and Multistage Amplifiers, Ch. 10 Frequency Response, Ch. 12 Output Stages and Power Amplifiers); P. R. Gray, P. J. Hurst, S. H. Lewis & R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. (Ch. 3–4 for the current-source-loaded pair).

How the figures were recovered. component placement, which terminal the input drives, and whether a load pair is a mirror or two independent sources. Where the printed data and the drawn topology cannot both be satisfied, the reading adopted is stated in a check note rather than silently chosen.

Question 2: Common-Emitter Stage — Mid-Band Gain and Both 3 dB Frequencies (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single npn common-emitter stage. The source $v_s$ reaches the base through $R_S$ and the coupling capacitor $C_1$; $R_1$ biases the base to ground; the collector load $R_L$ returns to $+V_{CC}$ and carries the output; the emitter is fed by the current source $I_{bias}$ and is held at AC ground by $C_2=\infty$.

Given data (Question 2)
Quantity	Symbol	Value
Current gain	$\beta$	$100$
Base–emitter drop	$V_{BE}$	$0.7\ \text{V}$
Saturation limit	$V_{CE(sat)}$	$0.3\ \text{V}$
Feedback capacitance	$C_\mu$	$2\ \text{pF}$
Source resistance	$R_S$	$600\ \Omega$
Collector load	$R_L$	$5\ \text{k}\Omega$
Base bias resistor	$R_1$	$1\ \text{k}\Omega$
Coupling / bypass capacitors	$C_1$, $C_2$	$10\ \mu\text{F}$, $\infty$
Emitter bias current	$I_{bias}$	$1\ \text{mA}$
Thermal voltage	$V_T$	$25\ \text{mV}$

Find. (a) the mid-band voltage gain $v_{OUT}/v_s$, (b) the lower 3 dB corner $f_L$, (c) the upper 3 dB corner $f_H$, and (d) the second high-frequency pole.

Question 2 — common-emitter stage. C₁ sets the low-frequency corner; C₂ = ∞ ties the emitter to AC ground at every frequency of interest.

Approach. Fix the DC operating point from $I_{bias}$, convert it to $g_m$ and $r_\pi$, take the mid-band gain as the input divider times the intrinsic gain, then treat the two frequency ends separately: the single finite low-frequency capacitor $C_1$ gives $f_L$ directly, while the Miller decomposition of $C_\mu$ produces the input pole asked for in (c) and the output pole asked for in (d).

Part (a) — DC operating point and hybrid-π parameters. The current source fixes the emitter current, so$$I_C=\alpha I_{bias}=\frac{\beta}{\beta+1}I_{bias}=\frac{100}{101}\times1\ \text{mA}=0.9901\ \text{mA}$$$$g_m=\frac{I_C}{V_T}=\frac{0.9901\ \text{mA}}{25\ \text{mV}}=39.60\ \text{mA/V},\qquad r_\pi=\frac{\beta}{g_m}=2.525\ \text{k}\Omega$$Checking the bias is legitimate: the collector sits at $V_C=V_{CC}-I_CR_L=10-4.95=5.05\ \text{V}$ and the emitter at about $-0.71\ \text{V}$, so $V_{CE}=5.76\ \text{V}$, comfortably above the stated $V_{CE(sat)}=0.3\ \text{V}$. The instruction to neglect $r_o$ means the quoted $V_A=100\ \text{V}$ is used only for this kind of plausibility check.
Mid-band gain. In the mid-band $C_1$ is a short and $C_\mu$ is an open, so the base is loaded by $R_1$ in parallel with $r_\pi$ and the source is divided down before it reaches $v_\pi$:$$R_1\parallel r_\pi=\frac{1.000\times2.525}{1.000+2.525}\ \text{k}\Omega=716.3\ \Omega,\qquad \frac{v_\pi}{v_s}=\frac{716.3}{600+716.3}=0.5442$$The emitter is at AC ground through $C_2$, so the intrinsic gain is the full $-g_mR_L=-39.60\ \text{mA/V}\times5\ \text{k}\Omega=-198.0$, and$$\boxed{A_M=\frac{v_{OUT}}{v_s}=-198.0\times0.5442=-107.8\ \text{V/V}}$$Almost half the available gain is lost in the input divider, because the $1\ \text{k}\Omega$ bias resistor is comparable with $r_\pi$.
Part (b) — the lower corner. With $C_2=\infty$ the emitter is grounded at all frequencies, so $C_1$ is the only capacitor that can produce a low-frequency pole. The resistance it faces is the series path it sits in:$$R_{C1}=R_S+(R_1\parallel r_\pi)=600+716.3=1316.3\ \Omega$$$$f_L=\frac{1}{2\pi R_{C1}C_1}=\frac{1}{2\pi\times1316.3\ \Omega\times10\ \mu\text{F}}=\boxed{12.09\ \text{Hz}}$$
Part (c) — Miller decomposition of the feedback capacitance. $C_\mu$ bridges base and collector across a gain of $-g_mR_L=-198.0$, so referred to the input it appears enlarged by that factor plus one:$$C_{in}=C_\mu\,(1+g_mR_L)=2\ \text{pF}\times199.0=398.0\ \text{pF}$$The resistance at the base node with the source active is$$R_{th}=R_S\parallel R_1\parallel r_\pi=600\parallel716.3=326.5\ \Omega$$so the dominant high-frequency pole, and hence the upper corner, is$$f_H\simeq\frac{1}{2\pi R_{th}C_{in}}=\frac{1}{2\pi\times326.5\ \Omega\times398.0\ \text{pF}}=\boxed{1.22\ \text{MHz}}$$Because $C_\mu$ is the only high-frequency capacitor in the model given, the exact transfer function has a single pole, and the open-circuit time-constant method returns it exactly: $R_{C\mu}=R_{th}(1+g_mR_L)+R_L=69.98\ \text{k}\Omega$, giving $1.14\ \text{MHz}$. The Miller estimate is 7 % high, which is the expected direction and size of the approximation and confirms the arithmetic.
Part (d) — the second high-frequency pole. The output half of the Miller decomposition places$$C_{out}=C_\mu\!\left(1+\frac{1}{g_mR_L}\right)=2\ \text{pF}\times1.005=2.010\ \text{pF}$$across the collector node, which is faced by $R_L$ alone once $r_o$ is neglected. Hence$$f_{p2}=\frac{1}{2\pi R_LC_{out}}=\frac{1}{2\pi\times5\ \text{k}\Omega\times2.010\ \text{pF}}=\boxed{15.8\ \text{MHz}}$$This sits a factor of 13 above $f_H$, which is what justifies calling the input pole dominant and taking $f_H\simeq f_{p1}$ in part (c). For completeness, the feed-forward path through $C_\mu$ also places a right-half-plane zero at $g_m/2\pi C_\mu=3.15\ \text{GHz}$, far enough away to be irrelevant here.

Final results — Question 2
Part	Quantity	Value
—	$I_C$, $g_m$, $r_\pi$	$0.990\ \text{mA}$, $39.60\ \text{mA/V}$, $2.525\ \text{k}\Omega$
(a)	Mid-band gain $v_{OUT}/v_s$	$-107.8\ \text{V/V}$ ($40.7$ dB)
(b)	Lower 3 dB frequency $f_L$	$12.1\ \text{Hz}$
(c)	Upper 3 dB frequency $f_H$	$1.22\ \text{MHz}$ (exact single pole $1.14\ \text{MHz}$)
(d)	Second high-frequency pole	$15.8\ \text{MHz}$

Topic. Mid-band gain and the two band edges of a common-emitter stage.

Key relations. $g_m=I_C/V_T$, $r_\pi=\beta/g_m$; $A_M=-g_mR_L\cdot\dfrac{R_1\parallel r_\pi}{R_S+R_1\parallel r_\pi}$; $f_L=1/2\pi C_1[R_S+(R_1\parallel r_\pi)]$; Miller $C_{in}=C_\mu(1+|A|)$, $C_{out}=C_\mu(1+1/|A|)$; open-circuit time constant $R_{C\mu}=R_{th}(1+g_mR_L)+R_L$.

Why this works. The two band edges are set by different capacitors facing different resistances, which is why they can be computed independently. At the low end $C_1$ is in series with the signal path, so it and the total series resistance form a high-pass corner; every other capacitor is either infinite or negligibly small there. At the high end the bridging capacitor $C_\mu$ is the whole story, and Miller’s theorem splits it into an input part that is amplified by the stage gain and an output part that is not. The input part is enormous because the gain is large, which is exactly why a common-emitter stage has poor bandwidth and why cascoding (Question 1) exists. Note that the split is an approximation: it assumes the gain across $C_\mu$ is still $-g_mR_L$ at the pole frequency, which is why the estimate lands a few percent away from the exact single pole.

Common pitfall. Forgetting the input divider in part (a) — quoting $-198$ instead of $-107.8$ — because $R_1$ looks like a bias component rather than a signal one. A second trap is using $R_L$ instead of $R_{th}$ for the input pole; the base node sees the source and bias resistances, not the collector load.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §10.1–10.4 (Frequency Response: low-frequency response, the Miller effect and the method of open-circuit time constants).

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