22-Elec-B5 Advanced Electronics · May 2015

Question 4 of 5: MOS Differential Pair with Current-Source Loads

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Question 4: MOS Differential Pair with Current-Source Loads (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. An n-channel source-coupled pair ($M_1$, $M_2$) driven differentially by $\pm v_{IN}/2$, with the tail returned to $-V_{EE}$ through the resistor $R$. The loads $M_3$ and $M_4$ are p-channel devices whose gates are tied together and taken to an external terminal $V_{bias}$ — neither is diode-connected, so they are two independent current sources, not a current mirror. The output is taken single-ended at the drain of $M_2$.

Find. (a) the single-ended differential gain $v_{OUT}/v_{IN}$, (b) the common-mode input resistance, (c) the common-mode input range, and (d) the CMRR in decibels.

Approach. The load gate bias fixes the branch current, which fixes every small-signal parameter; the differential gain then follows from the half circuit, the common-mode gain from the degenerated half circuit, and the input range from the saturation limits at the two ends.

1. Part (a) — operating point set by the load devices. $M_3$ and $M_4$ have $V_{SG}=V_{DD}-V_{bias}=2\ \text{V}$, so their overdrive is $|V_{OV,p}|=2-1=1\ \text{V}$ and each supplies$$I_D=\tfrac{1}{2}K|V_{OV,p}|^{2}=\tfrac{1}{2}\times0.5\ \text{mA/V}^2\times(1\ \text{V})^{2}=0.25\ \text{mA}$$The input devices therefore carry $0.25\ \text{mA}$ each, a tail current of $I_{SS}=0.5\ \text{mA}$, with$$V_{OV,n}=\sqrt{\frac{2I_D}{K}}=1.00\ \text{V},\qquad g_m=KV_{OV,n}=0.50\ \text{mA/V},\qquad r_o=\frac{1}{\lambda I_D}=200\ \text{k}\Omega$$
2. Differential gain from the half circuit. Under a purely differential drive the tail node is a virtual ground, so each side is a common-source stage loaded by its own $r_o$ in parallel with the load device’s $r_o$:$$R_{out}=r_{o2}\parallel r_{o4}=200\parallel200=100\ \text{k}\Omega$$The gate of $M_2$ is driven by only half the differential input, and because the loads are independent current sources the signal current from the $M_1$ side is not folded into the output node. Hence$$A_d=\frac{v_{OUT}}{v_{IN}}=\tfrac{1}{2}g_m\,(r_{o2}\parallel r_{o4})=\tfrac{1}{2}\times0.50\ \text{mA/V}\times100\ \text{k}\Omega$$which evaluates to$$\boxed{A_d=25\ \text{V/V}\;\;(28.0\ \text{dB})}$$The result is positive, because the output is taken at the drain of $M_2$ and that gate is driven by $-v_{IN}/2$; the magnitude is what the question asks for. Had $M_3$–$M_4$ been a true current mirror the answer would double to $50\ \text{V/V}$, which is why the drain-gate connection had to be checked on the drawing.
3. Part (b) — common-mode input resistance. Both inputs drive insulated MOS gates. At DC and at audio frequencies no current flows into either gate, so$$\boxed{R_{icm}\rightarrow\infty}$$This is the structural advantage of a MOS input pair over a bipolar one, where the equivalent figure is finite at $R_{icm}=\tfrac{1}{2}[r_\pi+(\beta+1)2R]$. In practice the input resistance is set by gate leakage (typically many $\text{G}\Omega$) and, at higher frequencies, by the gate capacitance rather than by anything in the small-signal model given here.
4. Part (c) — upper end of the common-mode range. Raising $V_{ICM}$ eventually pushes $M_1$ and $M_2$ out of saturation, which needs $V_D\ge V_{ICM}-V_{TN}$. The highest the drains can sit while the load devices stay saturated is $V_D=V_{DD}-|V_{OV,p}|=9\ \text{V}$, so$$V_{ICM,\max}=V_{DD}-|V_{OV,p}|+V_{TN}=10-1+1=\boxed{10\ \text{V}}$$
5. Lower end of the common-mode range. Going down, the tail node follows the inputs at $V_S=V_{ICM}-V_{GS}$ with $V_{GS}=V_{TN}+V_{OV,n}=2.00\ \text{V}$, and the tail resistor must still develop $I_{SS}R=0.5\ \text{mA}\times2\ \text{k}\Omega=1.00\ \text{V}$ above the negative rail. Hence$$V_{ICM,\min}=-V_{EE}+I_{SS}R+V_{GS}=-10+1.00+2.00=\boxed{-7.0\ \text{V}}$$so the pair accepts $-7.0\ \text{V}\le V_{ICM}\le10\ \text{V}$, a window $17\ \text{V}$ wide out of a $20\ \text{V}$ supply span.
6. Part (d) — common-mode gain. Under a common-mode drive the two halves move together, so each half circuit is a common-source stage degenerated by $2R=4\ \text{k}\Omega$ and loaded by $r_{o4}$. Including the device’s own output resistance,$$\begin{aligned}A_{cm}&=-\frac{g_mr_{o4}\,r_{o2}}{r_{o2}+r_{o4}+2R\,(1+g_mr_{o2})}\\&=-\frac{0.50\ \text{mA/V}\times200\times200\ (\text{k}\Omega)^{2}}{200+200+4(1+100)\ \text{k}\Omega}=-24.9\end{aligned}$$A direct three-node solve of the same circuit returns the tail node at $0.4975\,v_{icm}$ and the output at $-24.88\,v_{icm}$, confirming the closed form.
7. Common-mode rejection ratio. Dividing the two gains,$$\text{CMRR}=\left|\frac{A_d}{A_{cm}}\right|=\frac{25}{24.9}=1.005\;\;\Longrightarrow\;\;\boxed{\text{CMRR}=20\log_{10}(1.005)\approx0\ \text{dB}}$$This is not an arithmetic slip: the classical shortcut agrees, since $\text{CMRR}\simeq g_mR_{SS}=0.50\ \text{mA/V}\times2\ \text{k}\Omega=1$. A $2\ \text{k}\Omega$ resistive tail is simply far too small to reject anything against a $100\ \text{k}\Omega$ effective load: the common-mode gain is set by the ratio of load to tail impedance, and here that ratio is of the same order as the differential gain itself. Replacing $R$ with a saturated MOSFET tail of the same current, $R_{SS}=1/(\lambda I_{SS})=100\ \text{k}\Omega$, would lift the CMRR to about $28\ \text{dB}$; a cascoded tail or a mirror load would lift it much further. That contrast is the real lesson of the question.