22-Elec-B5 Advanced Electronics · May 2015

Question 5 of 5: Sizing the Output Coupling Capacitor of an Audio CS Stage

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2015 — 07-Elec-B5 Advanced Electronics. Three hours, CLOSED BOOK, any non-communicating calculator permitted. Five questions, 20 marks each; all five must be answered. The paper directs candidates to state any assumptions made, to treat ground and chassis as common, and to assume ideal op-amps on ±15 V rails unless a question says otherwise.

Reference texts. B. Razavi, Fundamentals of Microelectronics, 2nd ed. (Ch. 9, Cascode Stages and Current Mirrors — Question 1 cites Example 9.9 by name); A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (Ch. 8 Building Blocks of IC Amplifiers, Ch. 9 Differential and Multistage Amplifiers, Ch. 10 Frequency Response, Ch. 12 Output Stages and Power Amplifiers); P. R. Gray, P. J. Hurst, S. H. Lewis & R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. (Ch. 3–4 for the current-source-loaded pair).

How the figures were recovered. component placement, which terminal the input drives, and whether a load pair is a mirror or two independent sources. Where the printed data and the drawn topology cannot both be satisfied, the reading adopted is stated in a check note rather than silently chosen.

Question 5: Sizing the Output Coupling Capacitor of an Audio CS Stage (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single common-source stage on split $\pm5\ \text{V}$ rails. The gate is returned to ground through $R_G$ and driven directly by $v_{IN}$; the source sits on the unbypassed resistor $R_S$ to $-V_{SS}$; the drain load is $R_D$ to $+V_{DD}$; and the output reaches $R_L$ through the coupling capacitor $C_C$, which is the only capacitor in the circuit.

Given data (Question 5)
Quantity	Symbol	Value
Supply rails	$V_{DD} = \|V_{SS}\|$	$5\ \text{V}$
Transconductance parameter	$K_n$	$0.5\ \text{mA/V}^2$
Threshold voltage	$V_{TH}$	$1\ \text{V}$
Drain load	$R_D$	$6.7\ \text{k}\Omega$
Source resistor (unbypassed)	$R_S$	$5\ \text{k}\Omega$
Gate return	$R_G$	$50\ \text{k}\Omega$
External load	$R_L$	$10\ \text{k}\Omega$
Target lower corner	$f_L$	$20\ \text{Hz}$

Find. The value of $C_C$ that places the lower corner frequency of the amplifier at $20\ \text{Hz}$.

Question 5 — audio common-source stage. C-C is the only capacitor, so it alone sets the low-frequency corner; R-S is unbypassed and therefore does not appear in that time constant.

Approach. Establish the bias so the device is confirmed to be in saturation, identify the single high-pass time constant that $C_C$ forms with the resistance on either side of it, and invert the corner-frequency relation.

DC operating point. No gate current flows through $R_G$, so the gate sits at $0\ \text{V}$ and $V_{GS}=0-V_S=V_{DD}-I_DR_S$ with $V_S=-V_{SS}+I_DR_S$. Substituting into the saturation law gives one equation in $I_D$:$$I_D=\tfrac{1}{2}K_n\left(V_{DD}-I_DR_S-V_{TH}\right)^{2}$$With the numbers in mA and volts this is $6.25I_D^{\,2}-11I_D+4=0$, whose roots are $0.5134\ \text{mA}$ and $1.2466\ \text{mA}$. The larger root drives $V_{GS}$ below $V_{TH}$ and is rejected, so$$\boxed{I_D=0.513\ \text{mA}}$$
Confirm saturation, then find $g_m$. Back-substituting, $V_{GS}=5-0.5134\times5=2.433\ \text{V}$, so the overdrive is $V_{OV}=1.433\ \text{V}$. The terminal voltages are$$V_S=-5+2.567=-2.433\ \text{V},\qquad V_D=5-0.5134\times6.7=1.560\ \text{V},\qquad V_{DS}=3.99\ \text{V}$$Since $V_{DS}=3.99\ \text{V}$ exceeds $V_{OV}=1.43\ \text{V}$ the device is comfortably saturated, which is what licenses the square-law model used above. The transconductance follows from the formula the paper supplies:$$g_m=K_n(V_{GS}-V_{TH})=0.5\ \text{mA/V}^2\times1.433\ \text{V}=0.717\ \text{mA/V}$$
Identify the time constant $C_C$ belongs to. $C_C$ sits in series between the drain node and the load. Looking left from the capacitor one sees $R_D$ in parallel with the resistance looking into the drain, which is infinite because channel-length modulation is not specified for this question; looking right one sees $R_L$. The two are in series around the capacitor:$$R_{C_C}=R_D+R_L=6.7+10.0=16.7\ \text{k}\Omega$$Note that $R_S$ does not enter. It is unbypassed, so there is no capacitor across it to create a second corner, and $R_G$ does not enter either, because the source drives the gate node directly with no coupling capacitor in that path. A single capacitor means a single high-pass corner, and it is the corner the question specifies.
Solve for the capacitor. A single-pole high pass reaches $-3\ \text{dB}$ where the capacitive reactance equals the total series resistance:$$f_L=\frac{1}{2\pi R_{C_C}C_C}\;\;\Longrightarrow\;\;C_C=\frac{1}{2\pi f_LR_{C_C}}=\frac{1}{2\pi\times20\ \text{Hz}\times16.7\ \text{k}\Omega}$$$$\boxed{C_C=0.477\ \mu\text{F}\;\;(477\ \text{nF})}$$Back-substituting, $1/(2\pi\times16.7\ \text{k}\Omega\times0.4765\ \mu\text{F})=20.0\ \text{Hz}$, as required. A $0.47\ \mu\text{F}$ standard E12 part gives $f_L=20.3\ \text{Hz}$ and is the value that would actually be specified.
Interpret the word “maximum”. Increasing $C_C$ moves the corner down, so if the requirement is read as $f_L\le20\ \text{Hz}$ then $0.477\ \mu\text{F}$ is the smallest acceptable value and there is no upper bound. Taken as the equality the question states — the corner is to be at $20\ \text{Hz}$ — the value is unique, and that is what is boxed. For context, the stage’s mid-band gain is$$A_M=-\frac{g_m(R_D\parallel R_L)}{1+g_mR_S}=-\frac{0.717\ \text{mA/V}\times4.01\ \text{k}\Omega}{1+3.58}=-0.63\ \text{V/V}$$so the unbypassed $5\ \text{k}\Omega$ source resistor costs this “amplifier” all of its voltage gain; it is a linearised buffer rather than a gain stage, and a designer would bypass $R_S$ with a second capacitor if gain were wanted, at the price of a second low-frequency corner to place.

Final results — Question 5
Quantity	Value
Drain current $I_D$	$0.513\ \text{mA}$
Gate–source voltage / overdrive	$2.433\ \text{V}$ / $1.433\ \text{V}$
Terminal voltages $V_S$, $V_D$, $V_{DS}$	$-2.43\ \text{V}$, $1.56\ \text{V}$, $3.99\ \text{V}$ (saturated)
Transconductance $g_m$	$0.717\ \text{mA/V}$
Resistance in the $C_C$ loop	$16.7\ \text{k}\Omega$
Coupling capacitor $C_C$	$0.477\ \mu\text{F}$ (nearest standard value $0.47\ \mu\text{F}$)
Mid-band gain (context)	$-0.63\ \text{V/V}$

Topic. Coupling capacitors and the low-frequency corner of a discrete stage.

Key relations. Self-bias: $I_D=\tfrac{1}{2}K_n(V_{DD}-I_DR_S-V_{TH})^{2}$; $g_m=K_n(V_{GS}-V_{TH})$; saturation test $V_{DS}\ge V_{OV}$; single-pole corner $f_L=1/2\pi C_C(R_D+R_L)$; degenerated gain $A_M=-g_m(R_D\parallel R_L)/(1+g_mR_S)$.

Why this works. A coupling capacitor exists to pass signal while blocking the DC level difference between two nodes, and it does so imperfectly at low frequencies where its reactance becomes comparable with the resistance it works into. That resistance is whatever the capacitor sees looking both ways with the source set to zero, so a drain-to-load coupling capacitor sees the drain load in series with the external load. Because only one capacitor is present, the response is a clean single-pole high pass and the corner is exactly the reciprocal time constant; with several capacitors the corner would have to be estimated by short-circuit time constants, and the largest individual corner would dominate. Sizing for the bottom of the audio band is the design driver: 20 Hz is the conventional lower limit of hearing, and a corner placed there attenuates the lowest programme material by 3 dB.

Common pitfall. Including $R_S$ or $R_G$ in the time constant. $R_S$ is unbypassed, so it carries no capacitor and creates no corner; it does affect the gain, but not $f_L$. The other frequent error is choosing the wrong root of the bias quadratic — always back-substitute and confirm that $V_{GS}$ exceeds $V_{TH}$ and that $V_{DS}\ge V_{OV}$.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §7.3 (biasing discrete MOS amplifiers) and §10.1 (low-frequency response of a discrete-circuit amplifier).

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