Question 1 of 5: Class-B push–pull output stage — load power, device dissipation and efficiency

Question 1: Class-B push–pull output stage — load power, device dissipation and efficiency (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Find. The greatest sinusoidal power the stage can put into the 8 Ω load, the greatest average power that Q₁ itself has to get rid of (which is not at that same operating point), and the best conversion efficiency the stage can reach.

[Figure not reproduced: Question 1 — complementary class-B push–pull output stage as drawn on the exam paper. Q 1 (npn) sources current into R L on the positive half cycle and Q 2 (pnp) sinks it on the negative half; D 1 –D 2 and the two bias sources set the quiescent point only. See the official exam paper.]

Approach. Treat the stage as an ideal class-B pair — each transistor is an emitter follower that conducts one half-cycle of a half-sine load current — then evaluate the three standard half-cycle averages (load power, device dissipation, supply power) as functions of the output amplitude V̂_o and maximise each one separately.

1. Part (a) — fix the largest usable output amplitude. Q₁ is an npn emitter follower fed from +V_CC and Q₂ a pnp emitter follower fed from −V_EE; the diode string D₁–D₂ only sets the quiescent bias and carries no signal current. The output therefore follows the input until the conducting device saturates, so with V_CE,sat neglected $$\hat V_{o,\max} = V_{CC} = 10\ \text{V}.$$
2. Compute the maximum load power. For a sinusoid of amplitude V̂_o across R_L the average power is $P_L = \hat V_o^{\,2}/(2R_L)$. Substituting the amplitude found above, $$P_{L,\max} = \frac{(10\ \text{V})^{2}}{2(8\ \Omega)} = \boxed{6.25\ \text{W}}$$ which answers part (a).
3. Part (b) — write the dissipation of one device as a function of amplitude. Over the half cycle in which Q₁ conducts, the collector current is $i_C = (\hat V_o/R_L)\sin\theta$ and the voltage across the device is $v_{CE} = V_{CC} - \hat V_o\sin\theta$. Averaging their product over the full period (Q₁ is off for the other half) gives $$P_{D1} = \frac{1}{2\pi}\int_{0}^{\pi}\bigl(V_{CC}-\hat V_o\sin\theta\bigr) \frac{\hat V_o\sin\theta}{R_L}\,d\theta = \frac{V_{CC}\hat V_o}{\pi R_L} - \frac{\hat V_o^{\,2}}{4R_L}.$$
4. Maximise that expression over the output amplitude. Setting $dP_{D1}/d\hat V_o = V_{CC}/(\pi R_L) - \hat V_o/(2R_L) = 0$ gives the amplitude at which one transistor works hardest: $$\hat V_o\big|_{P_{D}\max} = \frac{2V_{CC}}{\pi} = \frac{2(10)}{\pi} = 6.366\ \text{V}.$$ This is only 64 % of the rail, so the hottest operating point is a partly driven stage, not a fully driven one — the red curve in the figure above.
5. Evaluate the peak device dissipation. Substituting $\hat V_o = 2V_{CC}/\pi$ back into the expression of step 3 collapses it to $$P_{D1,\max} = \frac{V_{CC}^{\,2}}{\pi^{2}R_L} = \frac{(10)^{2}}{\pi^{2}(8)} = \boxed{1.267\ \text{W}}$$ per transistor, which answers part (b). For comparison, at the full 10 V output of part (a) each device dissipates only $10(10)/(\pi\cdot 8) - 10^{2}/(4\cdot 8) = 0.854\ \text{W}$, so sizing the heatsink from the maximum-output condition would under-rate it by about 48 %.
6. Part (c) — supply power and efficiency. Each supply delivers the average of a half-sine of amplitude $\hat V_o/R_L$, so together the two rails deliver $P_S = 2V_{CC}\hat V_o/(\pi R_L)$ and $$\eta = \frac{P_L}{P_S} = \frac{\hat V_o^{\,2}/(2R_L)}{2V_{CC}\hat V_o/(\pi R_L)} = \frac{\pi}{4}\cdot\frac{\hat V_o}{V_{CC}}.$$ Efficiency rises linearly with drive, so it is greatest at the largest amplitude the stage can produce.
7. Evaluate the maximum efficiency. Putting $\hat V_o = V_{CC}$ into the result of step 6, $$\eta_{\max} = \frac{\pi}{4} = \boxed{78.5\ \text{percent}}$$ which answers part (c). At that point the rails supply $P_S = 2(10)(10)/(\pi\cdot 8) = 7.958\ \text{W}$ against 6.25 W in the load.
8. Cross-check the three results against a power balance. Whatever the amplitude, $P_S = P_L + 2P_{D}$ must hold. At the worst-case amplitude 6.366 V: 5.066 W supplied, 2.533 W in the load and $2 \times 1.267 = 2.533$ W in the devices. At full output: 7.958 W supplied, 6.250 W in the load and $2 \times 0.854 = 1.708$ W in the devices. Both balance exactly, so the three answers are mutually consistent.

Final Results