Question 2 of 5: Common-source amplifier — mid-band gain with and without the source bypass, and the resulting bandwidth
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, May 2016 — 07-Elec-B5
Advanced Electronics. Three hours, CLOSED BOOK; any non-communicating
calculator permitted. Answer all FIVE (5) questions; all questions
are worth 20 marks each. Ground and chassis are common in every schematic; op-amps
are ideal and supplies are ±15 V unless a question states otherwise.
Candidates are urged to state any interpretation assumption inside their answer
— this solution does so in the shaded Check callouts.
Reference texts.
A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. —
Ch. 7 (transistor amplifiers and the small-signal models), Ch. 8 (current mirrors
and the cascode), Ch. 10 (frequency response, Miller's theorem, open-circuit time
constants), Ch. 11 (feedback topologies and the effect on port resistances),
Ch. 12 (class-A/B output stages), Ch. 17 (tuned amplifiers).
B. Razavi, Fundamentals of Microelectronics, 2nd ed. — Ch. 9
(cascode stages; Example 9.9, p. 405 is cited by name in Question 3),
Ch. 11 (frequency response), Ch. 12 (feedback).
P. R. Gray, P. J. Hurst, S. H. Lewis & R. G. Meyer, Analysis and Design
of Analog Integrated Circuits, 5th ed. — Ch. 3 (single-stage amplifiers),
Ch. 7 (frequency response), Ch. 8 (feedback).
C. K. Alexander & M. N. O. Sadiku, Fundamentals of Electric Circuits,
7th ed. — Ch. 14 (resonance, bandwidth and quality factor).
Check — how the schematics below were obtained. Every question on this paper carries load-bearing data that exists only in the
drawing (which branch a reactance sits in, which terminal a source drives, whether
a bypass capacitor is present). Where the drawing is under-specified, the
reading adopted is stated in a Check callout inside that question rather
than being buried in the arithmetic.
Question 2: Common-source amplifier — mid-band gain with and without the source bypass, and the resulting bandwidth (20 marks)
Find. The mid-band gain with the source bypassed, the mid-band
gain once the bypass is deleted, and the upper 3 dB frequency of that degenerated
stage.
Question 2 — common-source equivalent circuit. Ibias is ideal, so the drain load is RL||ro; C2 bypasses Rs in part (a) and is deleted in parts (b) and (c).
Approach. Replace M1 by its small-signal model, note
that the ideal Ibias source is an open circuit so the only drain load is
RL in parallel with ro, obtain the two mid-band gains from
nodal analysis, then get fH from the sum of open-circuit time constants of
Cgs, Cgd and CL.
Establish what the signal sees at each terminal.
Ibias is an ideal current source, so it presents an open circuit to the
signal and contributes nothing to the drain load. C1 is a short at signal
frequencies and the gate draws no mid-band current, so no current flows in
Ri and the whole source voltage reaches the gate:
$v_I = v_i$ and $v_{gs} = v_i - v_s$.
Part (a) — gain with C2 in place. With
C2 = ∞ the source terminal is at signal ground, so
$v_{gs}=v_i$ and the drain drives $R_L\parallel r_o$:
$$A_{v,a} = -g_m\,(R_L\parallel r_o)
= -(2\ \text{mA/V})\left(\frac{20\times 20}{20+20}\ \text{k}\Omega\right)
= \boxed{-20.0\ \text{V/V}}$$
i.e. a gain magnitude of 20 (26.0 dB), inverting.
Part (b) — put the degeneration resistor back in. With
C2 gone, Rs carries the drain current and ro is no
longer in a simple parallel path, so the two node equations must be solved together.
Writing $i$ for the current leaving the drain terminal, the source node gives
$v_s = iR_s$ and the drain node gives $v_{OUT} = -iR_L$, while the device relation
$i = g_m(v_i-v_s) + (v_{OUT}-v_s)/r_o$ closes the system.
Solve for the degenerated gain. Eliminating
$v_s$ and $i$ from the three relations of step 3 gives the exact expression
$$A_{v,b} = \frac{v_{OUT}}{v_i}
= \frac{-g_m r_o R_L}{r_o + R_L + R_s + g_m r_o R_s}.$$
Substituting the data, the denominator is
$D = 20 + 20 + 1.5 + (2)(20)(1.5) = 101.5\ \text{k}\Omega$ and the numerator is
$-(2)(20)(20) = -800\ \text{k}\Omega$, so
$$A_{v,b} = \frac{-800}{101.5} = \boxed{-7.88\ \text{V/V}}$$
which answers part (b). Note how badly the familiar textbook shortcut
$-g_mR_L/(1+g_mR_s) = -40/4 = -10$ over-predicts here: it assumes
$r_o \gg R_L$, whereas ro and RL are equal in this circuit, so
the shortcut is 27 % optimistic.
Part (c) — set up the open-circuit time-constant method.
The three device capacitors are far too small to interact with C1 and
C2, so the upper corner is estimated from
$f_H \approx 1/(2\pi\sum_k R_k C_k)$, where each $R_k$ is the resistance seen by
capacitor $k$ with the other two open and the source killed. With
$v_i = 0$ the gate sees Ri to ground.
Resistance facing CL at the drain. Looking into the
drain, the transistor with its source degeneration appears as
$r_o + R_s(1+g_m r_o)$ in parallel with RL:
$$R_{C_L} = R_L \parallel \bigl[r_o + R_s(1+g_mr_o)\bigr]
= 20 \parallel \bigl[20 + 1.5(41)\bigr] = 20\parallel 81.5 = 16.06\ \text{k}\Omega.$$
The degeneration has raised the intrinsic drain resistance from 20 kΩ to
81.5 kΩ, but RL still dominates the node.
Resistance facing Cgd (the Miller path). Because
Cgd bridges the gate and the drain, its driving-point resistance is the
bridging form
$$R_{C_{gd}} = R_i\bigl(1+|A_{v,b}|\bigr) + R_{C_L}
= 20(1+7.882) + 16.06 = 193.7\ \text{k}\Omega,$$
an order of magnitude larger than either terminal resistance on its own. This is the
Miller multiplication that makes the smallest capacitor on the page the dominant one.
Resistance facing Cgs. Injecting a test current into
the gate and out of the source and solving the same two node equations as step 3
gives
$$R_{C_{gs}} = R_i - \frac{R_s\bigl(g_m r_o R_i - R_L - r_o\bigr)}{D},$$
with the same denominator $D = 101.5\ \text{k}\Omega$ as the gain. Substituting,
$R_s(g_mr_oR_i - R_L - r_o) = 1.5(800-20-20) = 1140\ \text{k}\Omega^2$, so
$R_{C_{gs}} = 20 - 1140/101.5 = 20 - 11.23 = 8.77\ \text{k}\Omega$ —
appreciably less than Ri, because the source terminal partly follows the
gate.
Sum the time constants and take the corner frequency.
The three contributions are
$\tau_{gs} = 8.77\ \text{k}\Omega \times 20\ \text{fF} = 0.175\ \text{ns}$,
$\tau_{gd} = 193.7\ \text{k}\Omega \times 5\ \text{fF} = 0.968\ \text{ns}$ and
$\tau_L = 16.06\ \text{k}\Omega \times 5\ \text{fF} = 0.080\ \text{ns}$, so
$\sum\tau = 1.224\ \text{ns}$ and
$$f_H \approx \frac{1}{2\pi\sum\tau} = \frac{1}{2\pi(1.224\ \text{ns})}
= \boxed{130\ \text{MHz}}$$
which answers part (c). Cgd alone accounts for 79 % of the
total even though it is one quarter the size of Cgs.
Cross-check against the exact transfer function. Solving the
three-node network with all three capacitors present and bisecting for the
−3 dB point returns 132.4 MHz, so the open-circuit estimate is 1.8
% low — the expected direction, since the method is a
conservative bound whenever one pole dominates.
Final Results
Part
Quantity
Result
(a)
Mid-band gain, source bypassed
−20.0 V/V (26.0 dB, inverting)
(b)
Mid-band gain, C2 removed
−7.88 V/V (17.9 dB)
(c)
Upper 3 dB frequency, C2 removed
fH ≈ 130 MHz
—
RCgs, RCgd, RCL
8.77 kΩ, 193.7 kΩ, 16.06 kΩ
—
Στ (dominated by Cgd)
1.224 ns
—
Exact −3 dB point (nodal solve)
132.4 MHz
Check — readings taken from the drawing.
(i) Ibias is drawn as an ideal current source with no output resistance
quoted, so it is treated as an open circuit; had a finite rbias been
specified it would sit in parallel with RL and lower both gains.
(ii) Ri is the resistance of the signal source, not a gate bias resistor
— the gate has no other d.c. path in the drawing, consistent with the
question's statement that biasing is already taken care of. That is why
vI = vi at mid-band but Ri still sets the
high-frequency behaviour. (iii) C2 is the source bypass and C1
the input coupling capacitor; both being infinite, they place no lower corner on the
response, so fH is the only bandwidth limit.