Question 3 of 5: Common-Emitter Amplifier — Sizing the Three Capacitors for a 100 Hz Lower Corner

Question 3: Common-Emitter Amplifier — Sizing the Three Capacitors for a 100 Hz Lower Corner (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Find. Values for $C_{C1}$, $C_{C2}$ and $C_E$ that place the lower −3 dB corner at 100 Hz, and a statement of which one dominates.

Approach. Use the short-circuit time-constant (SCTC) method: with all other capacitors shorted, find the resistance each capacitor sees, sum the resulting pole frequencies to estimate $f_L$, then allocate that budget across the three capacitors as an explicit design choice and round to preferred values.

1. State the method and note that the problem is under-determined. For a stage whose low-frequency response is set by several series capacitors, the SCTC estimate is $$\omega_L \;\approx\; \sum_i \frac{1}{R_i C_i}, \qquad f_L = \frac{1}{2\pi}\sum_i \frac{1}{R_i C_i},$$ where $R_i$ is the resistance seen by capacitor $i$ with every other capacitor replaced by a short. There is one specification and three unknowns, so the allocation of the 628.3 rad/s budget among the three poles is a design decision that must be stated, not derived. The consistency of the given data is worth checking first: $g_m r_\pi = 0.04 \times 2500 = 100 = \beta$, and $I_C = g_m V_T = 40\ \text{mA/V} \times 25\ \text{mV} = 1$ mA.
2. Find the resistance seen by the input coupling capacitor. With $C_E$ and $C_{C2}$ shorted, $C_{C1}$ looks into $R_S$ in series with the parallel combination of the bias divider and the transistor input resistance. With $R_B = R_{B1}\|R_{B2} = 180\|270 = 108\ \text{k}\Omega$, $$R_B \| r_\pi = \frac{108{,}000 \times 2500}{110{,}500} = 2.443\ \text{k}\Omega, \qquad R_{C_{C1}} = R_S + (R_B \| r_\pi) = 5 + 2.443 = 7.443\ \text{k}\Omega .$$
3. Find the resistance seen by the output coupling capacitor. Looking out from $C_{C2}$, the collector node presents $R_C$ (the transistor collector is an ideal current source at this level of modelling) and the load presents $R_L$, in series through the capacitor: $$R_{C_{C2}} = R_C + R_L = 8 + 5 = 13\ \text{k}\Omega .$$
4. Find the resistance seen by the emitter bypass capacitor. $C_E$ looks at $R_E$ in parallel with the resistance seen looking into the emitter, which is the base circuit divided by $\beta + 1$: $$R_{C_E} = R_E \;\Big\|\; \frac{r_\pi + (R_S \| R_B)}{\beta + 1}, \qquad R_S \| R_B = \frac{5 \times 108}{113} = 4.779\ \text{k}\Omega,$$ $$\frac{2500 + 4779}{101} = 72.07\ \Omega \quad\Longrightarrow\quad R_{C_E} = 2000 \,\|\, 72.07 = \boxed{\,69.56\ \Omega\,}$$ This is two orders of magnitude below the two coupling resistances, and that structural fact — not the allocation chosen next — is what makes $C_E$ the dominant element.
5. State and justify the allocation of the frequency budget. The defensible convention is to push the two coupling poles well clear of the corner and let the emitter capacitor define it. Placing each coupling pole a decade below the specification and giving the remainder to $C_E$: $$\omega_L = 2\pi(100) = 628.3\ \text{rad/s},\quad \omega_{C_{C1}} = \omega_{C_{C2}} = 2\pi(10) = 62.83\ \text{rad/s},$$ $$\omega_{C_E} = 628.3 - 2(62.83) = 502.7\ \text{rad/s}\ \ (f = 80\ \text{Hz}),$$ so the coupling capacitors take 10 % of the budget each and $C_E$ carries 80 %.
6. Convert each pole into a capacitance. $$C_{C1} = \frac{1}{R_{C_{C1}}\,\omega_{C_{C1}}} = \frac{1}{7443 \times 62.83} = 2.14\ \mu\text{F},$$ $$C_{C2} = \frac{1}{13{,}000 \times 62.83} = 1.22\ \mu\text{F}, \qquad C_E = \frac{1}{69.56 \times 502.7} = 28.6\ \mu\text{F},$$ $$\boxed{\;C_{C1} \approx 2.14\ \mu\text{F},\quad C_{C2} \approx 1.22\ \mu\text{F}, \quad C_E \approx 28.6\ \mu\text{F}\;}$$ Recombining the three poles returns 628.3 rad/s exactly, confirming the arithmetic.
7. Answer the question actually asked: which capacitor dominates? $C_E$ dominates. Its pole sits at 80 Hz against 10 Hz for each coupling capacitor, and it is more than twenty times larger in value, because it works into 69.6 Ω while the coupling capacitors work into 7.4 kΩ and 13 kΩ. This is generic to the topology: bypassing an emitter means driving the low resistance looking into the emitter, so $C_E$ is always the physically largest and electrically dominant capacitor in a bypassed common-emitter stage.
8. Round to preferred values and confirm the specification is still met. Capacitors come in E12 steps, and a lower corner is safe on the low side, so round each value up: $C_{C1} = 2.2\ \mu\text{F}$, $C_{C2} = 1.2\ \mu\text{F}$, $C_E = 33\ \mu\text{F}$. These give $$f_L = \frac{1}{2\pi}\left(\frac{1}{7443 \times 2.2\mu} + \frac{1}{13{,}000 \times 1.2\mu} + \frac{1}{69.56 \times 33\mu}\right) = 89.3\ \text{Hz},$$ comfortably inside the 100 Hz requirement. Two cross-checks close the answer out: the mid-band gain of the stage is $g_m (R_C\|R_L)\,(R_B\|r_\pi)/[R_S + (R_B\|r_\pi)] = 40.4$ V/V (32.1 dB), and an exact four-node solve of the full network with the computed capacitors puts the true −3 dB point at 90.1 Hz rather than 100 Hz. The SCTC sum always over-estimates $f_L$ when the poles are not widely separated, so designing to it is conservative by about 11 % here.