Question 5 of 5: Two-Stage Series–Shunt Feedback Amplifier — Feedback Factor, Loop Gain and Closed-Loop Gain

Question 5: Two-Stage Series–Shunt Feedback Amplifier — Feedback Factor, Loop Gain and Closed-Loop Gain (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Two n-channel common-source stages: $M_1$ driven at its gate by $v_S$ (through the DC level source $V_{GG}$), drain load $R_{D1}$, source returned to ground through $R_1$; $M_2$ takes the drain of $M_1$ at its gate, has its source grounded and its drain loaded by $R_{D2}$, and the output $v_O$ is taken at that drain. $R_2$ runs from $v_O$ back to the source of $M_1$. For part (d), $g_{m1} = g_{m2} = 4$ mA/V and $R_{D1} = R_{D2} = 10\ \text{k}\Omega$, with $R_1 = 1\ \text{k}\Omega$ and the $R_2$ found in part (b). The output resistances of both devices are neglected as the question directs.

Find. (a) the identity of the feedback network, expressions for $\beta$ and for the ideal $A_f$; (b) $R_2/R_1$ and $R_2$ for an ideal gain of 10 V/V; (c) an expression for the loop gain $A\beta$; (d) numerical values of $A\beta$, $A$ and $A_f$.

Approach. Identify the sampling and mixing at the two ports, read $\beta$ off the divider, then build the loaded forward amplifier $A$ by placing $R_1\|R_2$ in series at the input port and $R_1 + R_2$ in shunt at the output port. Combine as $A_f = A/(1+A\beta)$ and corroborate against a direct nodal solve of the real circuit.

1. Part (a): identify the topology from where the feedback network connects. $R_2$ connects to the output node $v_O$, so the network senses the output voltage in shunt. At the input end, $R_1$ and $R_2$ meet at the source of $M_1$, and the gate–source loop of $M_1$ therefore sees $v_{gs1} = v_S - v_f$ — the fed-back signal appears in series with the input. The topology is series–shunt, i.e. a voltage–voltage amplifier, which is the configuration that raises input resistance, lowers output resistance and stabilises voltage gain.
2. Write the feedback factor of the divider. The feedback network is the resistive divider $R_1$–$R_2$ loaded lightly by the source of $M_1$. Opening the input loop, the fraction of the output returned to the source node is $$\boxed{\;\beta = \frac{v_f}{v_o} = \frac{R_1}{R_1 + R_2}\;}$$
3. State the ideal (upper-bound) closed-loop gain. When the loop gain is large the closed-loop gain is set entirely by the passive network: $$A_f = \frac{A}{1 + A\beta} \;\xrightarrow[\;A\beta \gg 1\;]{}\; \frac{1}{\beta} \quad\Longrightarrow\quad \boxed{\;A_{f,\text{ideal}} = \frac{R_1 + R_2}{R_1} = 1 + \frac{R_2}{R_1}\;}$$ This is the familiar non-inverting-amplifier form, and it is an upper bound because a finite loop gain always leaves $A_f$ slightly below $1/\beta$.
4. Part (b): solve the divider for a design gain of 10 V/V. $$1 + \frac{R_2}{R_1} = 10 \quad\Longrightarrow\quad \boxed{\;\frac{R_2}{R_1} = 9\;} \qquad\text{and with } R_1 = 1\ \text{k}\Omega,\quad \boxed{\;R_2 = 9\ \text{k}\Omega\;}$$
5. Part (c): load the forward amplifier with the feedback network before writing $A$. The two-port treatment of a series–shunt loop charges the feedback network's loading to the basic amplifier: at the input port the network appears as $R_1 \| R_2$ in series with the source of $M_1$ (found by shorting the output port), and at the output port it appears as $R_1 + R_2$ in shunt with $R_{D2}$ (found by opening the input loop). Stage 1 is therefore a degenerated common-source stage and stage 2 a plain one: $$A_1 = -\frac{g_{m1}R_{D1}}{1 + g_{m1}(R_1\|R_2)}, \qquad A_2 = -g_{m2}\bigl[R_{D2} \| (R_1 + R_2)\bigr].$$
6. Assemble the open-loop gain and the loop gain. Cascading the two inverting stages gives a positive forward gain, as a series–shunt loop requires, and multiplying by $\beta$ gives the loop gain: $$\boxed{\;A = \frac{g_{m1}g_{m2}\,R_{D1}\bigl[R_{D2}\|(R_1+R_2)\bigr]}{1 + g_{m1}(R_1\|R_2)}, \qquad A\beta = A\,\frac{R_1}{R_1+R_2}\;}$$
7. Part (d): evaluate the loading terms. With $R_1 = 1\ \text{k}\Omega$ and $R_2 = 9\ \text{k}\Omega$, $$R_1 \| R_2 = \frac{1 \times 9}{10} = 900\ \Omega, \qquad R_1 + R_2 = 10\ \text{k}\Omega, \qquad \beta = \frac{1}{10} = 0.100 .$$
8. Evaluate the two stage gains and the open-loop gain. $$A_1 = -\frac{(4\ \text{mA/V})(10\ \text{k}\Omega)}{1 + (4\ \text{mA/V})(900\ \Omega)} = -\frac{40}{4.6} = -8.696,$$ $$R_{D2}\|(R_1+R_2) = 10\text{k}\|10\text{k} = 5\ \text{k}\Omega, \qquad A_2 = -(4\ \text{mA/V})(5\ \text{k}\Omega) = -20.0,$$ $$A = A_1 A_2 = (-8.696)(-20.0) = \boxed{\,174\ \text{V/V}\,}$$
9. Evaluate the loop gain and the closed-loop gain. $$A\beta = 173.9 \times 0.100 = \boxed{\,17.4\;} \qquad A_f = \frac{A}{1 + A\beta} = \frac{173.9}{18.39} = \boxed{\,9.46\ \text{V/V}\,}$$ The result sits 5.4 % below the ideal 10 V/V, which is the expected shortfall for a loop gain of only 17.4: rearranging, $A_f = (1/\beta)\,T/(1+T)$ with $T = A\beta$, so the fractional error is $1/(1+T) = 5.4$ %. A direct three-node solve of the actual circuit — no two-port decomposition, no loading approximations — returns 9.458 V/V, agreeing with the two-port answer to 0.01 %, which validates the loading rules used in Step 5. If the specification really demanded 10.0 V/V, the designer would either raise the loop gain (larger $g_m$ or $R_D$) or pre-distort the divider to $\beta = 0.0946$.