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22-Elec-B5 Advanced Electronics · December 2017

Question 4 of 5: Common-Source Amplifier — Mid-Band Gain With and Without the Source Bypass, and the New $f_H$

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams December 2017, 16-Elec-B5 Advanced Electronics — 3 hours, CLOSED BOOK, one approved Casio or Sharp calculator. Five questions, all to be answered, 20 marks each (100 marks total). In schematics ground and chassis are common; op-amps are ideal and supply rails are ±15 V unless stated otherwise. Candidates are instructed to state any interpretive assumption inside the answer, and to provide block diagrams and schematics wherever an essay-format response needs them.

Reference texts. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. (Ch. 7 transistor amplifiers, Ch. 8 cascodes and current mirrors, Ch. 10 frequency response, Ch. 11 feedback); B. Razavi, Fundamentals of Microelectronics, 2nd ed. (Ch. 9 cascode stages and current mirrors) and Design of Analog CMOS Integrated Circuits, 2nd ed. (Ch. 6 frequency response); R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, 5th ed. (Ch. 17 low-frequency response); P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. (Ch. 8 feedback).

How each answer is laid out. Every calculation question states its data, the quantity sought, the circuit as drawn on the paper, a one-line strategy, then numbered steps with the governing relation, the substitution and the intermediate result. Boxed values are the answers a marker looks for, and each question closes with a results table and a concept note.

Question 4: Common-Source Amplifier — Mid-Band Gain With and Without the Source Bypass, and the New $f_H$ (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

QuantityValue
Transconductance$g_m = 2\ \text{mA/V}$
Device output resistance$r_o = 20\ \text{k}\Omega$
Source resistance of the driver$R_i = 20\ \text{k}\Omega$
Load resistance$R_L = 20\ \text{k}\Omega$
Source-leg resistor$R_S = 3\ \text{k}\Omega$
Gate–source capacitance$C_{gs} = 20\ \text{fF}$
Gate–drain capacitance$C_{gd} = 5\ \text{fF}$
Load capacitance$C_L = 5\ \text{fF}$
Coupling / bypass$C_1 = C_2 = \infty$ (short at all signal frequencies)
+V DDI biasv iR iC 1v 1M 1v OUTR LC LR sC 2
Q4 as drawn on the paper: a common-source stage biased by an ideal current source $I_{bias}$, loaded by $R_L \| C_L$, and driven from $v_i$ through $R_i$ and the infinite coupling capacitor $C_1$. $C_2$ bypasses the source-leg resistor $R_S$.

Find. (a) the mid-band gain with $C_2$ in place, (b) the mid-band gain once $C_2$ is removed, and (c) the resulting upper −3 dB frequency.

Approach. With $C_2$ present the source is an AC ground, so part (a) is the textbook common-source result. Removing $C_2$ degenerates the stage, and because $r_o$ is comparable with $R_L$ the exact expression — not the $r_o \to \infty$ shortcut — is required. Part (c) then uses open-circuit time constants, evaluating each driving-point resistance on the degenerated network.

  1. Part (a): with $C_2$ fitted, the source is an AC ground. $C_2$ is specified as infinite, so it shorts $R_S$ at signal frequencies and the transistor sees its full transconductance into the parallel load. The gate node carries no current at mid-band (all capacitances are open), so no signal is lost across $R_i$ and $v_1 = v_i$: $$r_o \| R_L = \frac{20 \times 20}{40} = 10\ \text{k}\Omega, \qquad \frac{v_{OUT}}{v_i} = -g_m\,(r_o \| R_L) = -(2\ \text{mA/V})(10\ \text{k}\Omega) = \boxed{\,-20.0\ \text{V/V}\,}$$
  2. Part (b): removing $C_2$ puts $R_S$ into the signal path. The source node is now free to move, so a series–series feedback loop closes around the device. Writing KCL at the drain and source nodes of the small-signal model and eliminating the source voltage gives the exact degenerated result, in which the denominator $D$ collects every path from drain to ground: $$\frac{v_{OUT}}{v_i} = -\,\frac{g_m r_o R_L}{\,r_o + R_L + R_S + g_m r_o R_S\,} \equiv -\,\frac{g_m r_o R_L}{D}.$$
  3. Evaluate the degenerated gain. $$D = 20{,}000 + 20{,}000 + 3000 + (2\times10^{-3})(20{,}000)(3000) = 163\ \text{k}\Omega,$$ $$\frac{v_{OUT}}{v_i} = -\frac{(2\times10^{-3})(20{,}000)(20{,}000)}{163{,}000} = \boxed{\,-4.91\ \text{V/V}\,}$$ The 3 kΩ source resistor has cost a factor of four in gain. Note that the familiar shortcut $-g_m R_L/(1+g_m R_S) = -5.71$ V/V is 16 % high here, because it assumes $r_o \to \infty$ while the given $r_o$ is the same size as $R_L$; the exact form keeps the $(R_L + R_S)/r_o$ contribution and must be used.
  4. Part (c): choose the method and list the three capacitors. The stage has three capacitances and no dominant one is obvious, so use the method of open-circuit time constants: $$f_H \;\approx\; \frac{1}{2\pi\left(R_{C_{gs}}C_{gs} + R_{C_{gd}}C_{gd} + R_{C_L}C_L\right)},$$ where each $R$ is the resistance seen by that capacitor with the other two open-circuited and the independent source killed (so the gate returns to ground through $R_i$).
  5. Find the resistance seen by $C_{gd}$, which the Miller effect makes the largest. $C_{gd}$ bridges gate and drain, so it sees the gate-side resistance multiplied by one plus the stage gain, plus the drain-side resistance. Looking back into the drain of a degenerated device, $R_S$ is boosted by the intrinsic gain: $$R_d = R_L \,\Big\|\, \bigl[r_o + R_S(1 + g_m r_o)\bigr] = 20\text{k} \,\|\, \bigl[20\text{k} + 3\text{k}(41)\bigr] = 17.55\ \text{k}\Omega,$$ $$R_{C_{gd}} = R_i\bigl(1 + |A_v|\bigr) + R_d = 20\text{k}(1 + 4.908) + 17.55\text{k} = 135.7\ \text{k}\Omega .$$
  6. Find the resistance seen by $C_{gs}$ from the exact nodal expression. With the source degenerated the textbook $(R_i + R_S)/(1 + g_m R_S)$ is again an $r_o \to \infty$ form and is wrong by a large factor. The exact driving-point resistance between gate and source reuses the same denominator $D$ as the gain: $$R_{C_{gs}} = R_i - \frac{R_S\,(g_m r_o R_i - R_L - r_o)}{D} = 20\text{k} - \frac{3\text{k}\,(800\text{k} - 40\text{k})}{163\text{k}} = 6.01\ \text{k}\Omega,$$ against 5.38 kΩ from the shortcut. A three-by-three nodal driving-point solve of the same network returns 6.0123 kΩ, confirming the closed form.
  7. Find the resistance seen by $C_L$. $C_L$ sits from the drain to ground, and with $C_{gs}$ and $C_{gd}$ open the gate carries no current and rests at ground potential through $R_i$. The resistance is therefore the same drain-side quantity computed in Step 5: $$R_{C_L} = R_L \,\Big\|\, \bigl[r_o + R_S(1 + g_m r_o)\bigr] = 17.55\ \text{k}\Omega .$$
  8. Sum the time constants and report $f_H$. $$\sum R_i C_i = (6012)(20\ \text{fF}) + (135{,}706)(5\ \text{fF}) + (17{,}546)(5\ \text{fF})$$ $$= 0.1202 + 0.6785 + 0.0877 = 0.8865\ \text{ns},$$ $$f_H \approx \frac{1}{2\pi(0.8865\ \text{ns})} = \boxed{\,180\ \text{MHz}\,}$$ $C_{gd}$ carries 76.5 % of the total even though it is the smallest capacitor, purely because the Miller multiplication puts 136 kΩ behind it — the practical lesson of the question.
  9. Cross-check the estimate against an exact frequency sweep. Solving the full three-node network with all three capacitors and bisecting on $|H(f)|$ places the true −3 dB point at 184.8 MHz, so the OCTC estimate is 2.9 % low. That sign is expected and welcome: summing open-circuit time constants always over-estimates the total delay and therefore under-estimates $f_H$, making the design conservative. The mid-band value returned by the same network is 4.908, matching part (b) exactly.

Check: the ideal bias source and the reference for the gain. $I_{bias}$ is drawn as an ideal current source, so it is an open circuit to signal and contributes no conductance at the drain; if a real cascoded source were intended its output resistance would appear in parallel with $R_L$ and would lower both the gain and $R_d$. The question asks for $v_{OUT}/v_i$ rather than $v_{OUT}/v_1$, but with $C_1$ infinite and the gate drawing no mid-band current the two are identical, so no input divider appears in parts (a) and (b). At high frequency that is no longer true, which is precisely why $R_i$ enters the Miller term in part (c).

QuantityValue
$r_o \| R_L$$10.0\ \text{k}\Omega$
(a) Mid-band gain, $C_2$ fitted$\mathbf{-20.0\ \text{V/V}}$
Denominator $D$$163\ \text{k}\Omega$
(b) Mid-band gain, $C_2$ removed$\mathbf{-4.91\ \text{V/V}}$
Resistance seen by $C_{gs}$$6.01\ \text{k}\Omega$
Resistance seen by $C_{gd}$$135.7\ \text{k}\Omega$
Resistance seen by $C_L$$17.55\ \text{k}\Omega$
Sum of open-circuit time constants$0.8865\ \text{ns}$
(c) Upper corner $f_H$$\mathbf{180\ \text{MHz}}$
Exact −3 dB point (nodal sweep)$184.8\ \text{MHz}$ (OCTC 2.9 % low)
Dominant capacitor$C_{gd}$ — 76.5 % of the total time constant