Single-Stage CMOS Differential Amplifier — Device Sizing and Differential Gain: 22-Elec-B5 Advanced Electronics, May 2017, Q1

Question 1: Single-Stage CMOS Differential Amplifier — Device Sizing and Differential Gain (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A symmetric NMOS differential pair $M_1$–$M_2$ with matched PMOS loads $M_3$–$M_4$, all four devices biased in saturation at the same overdrive, in a 0.18 µm process:

Question 1 — given data
Quantity	Symbol	Value
Supply rails	$V_{DD} = \|V_{SS}\|$	1.5 V
Threshold magnitude	$\|V_{TH}\|$	0.5 V
Channel length (all devices)	$L$	0.36 µm
n-channel process transconductance	$\mu_n C_{ox}$	400 µA/V$^{2}$
p-channel process transconductance	$\mu_p C_{ox}$	100 µA/V$^{2}$ (one quarter of $\mu_n C_{ox}$)
Channel-length modulation	$\lambda$	0.2 V$^{-1}$
Tail current	$I_{bias}$	200 µA
Overdrive, all transistors	$\|V_{ov}\|$	0.2 V

Find. (a) the aspect ratios $W/L$ of $M_1$ to $M_4$ that deliver the specified overdrive at the specified bias current, and (b) the small-signal differential voltage gain $v_{do}/v_{id}$ measured between the two drains.

Question 1 — NMOS pair $M_1$/$M_2$ with a tail source $I_{bias}$ and matched PMOS loads $M_3$/$M_4$ whose common gate is held at the external bias $V_{G1}$. The output $v_{do}$ is taken differentially between the two drains, positive at the drain of $M_2$.

Approach. Split the tail current equally between the two branches, invert the saturation-region square law once for each device type to obtain the aspect ratios, then evaluate $g_m$ and $r_o$ at that operating point and apply the differential half-circuit.

Part (a) — share the tail current between the two branches. The pair is balanced, so the tail current divides equally:$$I_{D1} = I_{D2} = I_{D3} = I_{D4} = \frac{I_{bias}}{2} = \frac{200\ \mu\text{A}}{2} = 100\ \mu\text{A}$$Every device therefore carries 100 µA, and the loads must carry exactly what the pair draws or the drain nodes would drift to a rail.
Invert the square law for the n-channel pair. In saturation, and neglecting the $(1+\lambda v_{DS})$ correction for sizing, $I_D = \tfrac{1}{2}\mu_n C_{ox}\left(\dfrac{W}{L}\right)V_{ov}^{2}$, so$$\left(\frac{W}{L}\right)_{1,2} = \frac{2I_D}{\mu_n C_{ox}\,V_{ov}^{2}} = \frac{2(100\ \mu\text{A})}{(400\ \mu\text{A/V}^{2})(0.2\ \text{V})^{2}} = \boxed{12.5}$$With the fixed $L = 0.36\ \mu\text{m}$ this is a gate width $W_{1,2} = 12.5 \times 0.36 = 4.5\ \mu\text{m}$.
Repeat for the p-channel loads, which are four times weaker. The data give $\mu_n C_{ox} = 4\mu_p C_{ox}$, hence $\mu_p C_{ox} = 100\ \mu\text{A/V}^{2}$, and the same overdrive must be produced by a device with one quarter of the transconductance parameter:$$\left(\frac{W}{L}\right)_{3,4} = \frac{2I_D}{\mu_p C_{ox}\,V_{ov}^{2}} = \frac{2(100\ \mu\text{A})}{(100\ \mu\text{A/V}^{2})(0.2\ \text{V})^{2}} = \boxed{50}$$so $W_{3,4} = 50 \times 0.36 = 18\ \mu\text{m}$, four times the width of the n-channel devices — the usual price of a p-channel load. Each transistor sits at $|V_{GS}| = |V_{TH}| + |V_{ov}| = 0.7$ V, which leaves ample room between the $\pm 1.5$ V rails for both the tail source and the load overdrive.
Part (b) — evaluate the transconductance at that operating point. For a saturated MOSFET $g_m = 2I_D/V_{ov}$, and because every device shares the same current and the same overdrive, all four transconductances are equal:$$g_m = \frac{2I_D}{V_{ov}} = \frac{2(100\ \mu\text{A})}{0.2\ \text{V}} = 1.00\ \text{mA/V}$$This is the whole point of specifying the overdrive rather than the width: $g_m$ is fixed by $I_D$ and $V_{ov}$ alone.
Evaluate the small-signal output resistance of each device. The data give the channel-length-modulation parameter directly, so$$V_A = \frac{1}{\lambda} = 5\ \text{V}, \qquad r_o = \frac{1}{\lambda I_D} = \frac{V_A}{I_D} = \frac{5\ \text{V}}{100\ \mu\text{A}} = 50\ \text{k}\Omega$$and the same value applies to $M_1$–$M_4$ because $\lambda$ and $I_D$ are common to all of them.
Apply the differential half-circuit. For a differential input the tail node is a virtual ground, so each side reduces to a common-source stage loaded by its own $r_o$ in parallel with the load device's $r_o$. Taking the output between the two drains doubles the single-ended swing and also doubles the input, so the two factors of two cancel and$$A_d = \frac{v_{do}}{v_{id}} = g_m\,(r_{o2}\parallel r_{o4}) = (1.00\ \text{mA/V})\left(\frac{50 \times 50}{50+50}\ \text{k}\Omega\right) = \boxed{25\ \text{V/V}}$$or $20\log_{10} 25 = 28.0$ dB.
Check the result against the intrinsic gain. The largest voltage gain a single device can give is $g_m r_o = (1.00\ \text{mA/V})(50\ \text{k}\Omega) = 50$. Loading the pair with an equally long p-channel device halves that figure, and $A_d = 25$ is exactly one half, which confirms both the arithmetic and the topology. Had the output been taken single-ended from one drain against ground, the answer would be $v_{d2}/v_{id} = \tfrac{1}{2}g_m(r_{o2}\parallel r_{o4}) = 12.5$ V/V.

Check: the gates of $M_3$ and $M_4$ are tied to one another and taken out to the terminal marked $V_{G1}$; the exam figure shows no drain-to-gate short on $M_3$, so the loads are two matched current sources set by an external bias, not an active current mirror. Because the question asks for the gain between the two drains, the distinction does not change the answer — $A_d = g_m(r_{o2}\parallel r_{o4})$ holds for either reading. It would matter for a single-ended output, where a mirror recombines the two signal currents and returns $g_m(r_{o2}\parallel r_{o4})$ instead of half that value. The sizing also assumes $V_{DS}$ close enough to $V_{ov}$ that the $(1+\lambda v_{DS})$ factor may be dropped, which is standard practice and changes $W/L$ by only a few per cent.

Final results
Quantity	Symbol	Result
Drain current per branch	$I_D$	100 µA
Aspect ratio of $M_1$, $M_2$	$(W/L)_{1,2}$	12.5 ($W = 4.5$ µm)
Aspect ratio of $M_3$, $M_4$	$(W/L)_{3,4}$	50 ($W = 18$ µm)
Transconductance, all devices	$g_m$	1.00 mA/V
Early voltage / output resistance	$V_A$, $r_o$	5 V, 50 k$\Omega$
Effective drain load	$r_{o2}\parallel r_{o4}$	25 k$\Omega$
Differential gain	$v_{do}/v_{id}$	25 V/V (28.0 dB)
Single-ended gain (for reference)	$v_{d2}/v_{id}$	12.5 V/V

Topic. Sizing and gain of a CMOS differential pair with current-source loads.

Key relations. Saturation square law $I_D = \tfrac{1}{2}\mu C_{ox}(W/L)V_{ov}^{2}$; $g_m = 2I_D/V_{ov} = \sqrt{2\mu C_{ox}(W/L)I_D}$; $r_o = 1/(\lambda I_D) = V_A/I_D$; differential half-circuit gain $A_d = g_m(r_{on}\parallel r_{op})$; intrinsic gain $g_m r_o = 2V_A/V_{ov}$.

Why this works. Specifying the overdrive rather than the width fixes the small-signal behaviour before any geometry is chosen: $g_m$ follows from $I_D$ and $V_{ov}$, and $r_o$ follows from $I_D$ and $\lambda$, so the gain is settled by the bias point alone. The width is then whatever the square law demands to reach that overdrive, and it is here that the process asymmetry appears — a p-channel device needs four times the width of an n-channel device for the same current and overdrive because holes are roughly four times less mobile than electrons. The half-circuit is legitimate because a purely differential drive leaves the tail node at signal ground, which decouples the two branches completely.

Common pitfall. Two errors recur. The first is sizing the transistors with the full tail current instead of $I_{bias}/2$, which halves every aspect ratio. The second is forgetting that the load device contributes its own $r_o$ in parallel, so the pair delivers half of the intrinsic gain $g_m r_o$, not all of it; a related slip is quoting the single-ended value when the figure clearly defines $v_{do}$ across both drains.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §8.2 and §9.5 (MOS differential pair, active loads); Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., Ch. 4.

Question 1 of 5: Single-Stage CMOS Differential Amplifier — Device Sizing and Differential Gain

Question 1: Single-Stage CMOS Differential Amplifier — Device Sizing and Differential Gain (20 marks)