Question 1 of 5: MOS Differential Amplifier — Bias, Transconductance, Full Current Switching and Input Offset

Question 1: MOS Differential Amplifier — Bias, Transconductance, Full Current Switching and Input Offset (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Find. The quiescent gate–source voltages and transconductances of $M_1$ and $M_2$, the differential input that switches the whole tail current into one side, and the input offset voltage produced first by a 2 per cent load-resistor mismatch and then by a 2 per cent threshold mismatch.

Approach. Work the quiescent point first from the square-law saturation model at $I_{D}=I_{bias}/2$ per side, then obtain the full-switching input from the condition that one device carries the entire tail current while the other sits exactly at cut-off; the two offset parts follow by asking what differential input restores a balanced output when one parameter is perturbed.

1. Part (a) — collapse the process data into one device constant. The formula sheet defines the device transconductance parameter as $$K = \mu C_{ox}\left(\frac{W}{L}\right) = 20\ \frac{\mu\text{A}}{\text{V}^2}\times\frac{120\ \mu\text{m}}{6\ \mu\text{m}} = 20\times 20 = 400\ \mu\text{A/V}^2 .$$ Because both transistors are drawn identically and share the same threshold, this single number describes each side of the pair.
2. Split the tail current and solve for the overdrive. With $v_{I1}=v_{I2}$ the pair is balanced, the two sources sit at a common potential, and each device carries half the tail current, $I_{D1}=I_{D2}=I_{bias}/2 = 10\ \mu\text{A}$. Inverting the saturation law $I_D=\tfrac12 K V_{ov}^2$ gives $$V_{ov}=\sqrt{\frac{2I_D}{K}}=\sqrt{\frac{2\,(10\ \mu\text{A})}{400\ \mu\text{A/V}^2}}=\sqrt{0.05}=0.2236\ \text{V}.$$ Adding the threshold gives the quiescent gate–source voltage of each device, $$\boxed{V_{GS1}=V_{GS2}=V_{TH}+V_{ov}=1+0.2236=1.224\ \text{V}}$$
3. Evaluate the small-signal transconductance of each device. Differentiating the same square law, $g_m=\partial i_D/\partial v_{GS}=K V_{ov}$, and the three equivalent forms all agree, which is the free check on Step 2: $$\begin{aligned} g_m &= K V_{ov} = (400\ \mu\text{A/V}^2)(0.2236\ \text{V}) = 89.44\ \mu\text{A/V},\\ g_m &= \frac{2I_D}{V_{ov}} = \frac{2\,(10\ \mu\text{A})}{0.2236\ \text{V}} = 89.44\ \mu\text{A/V},\\ g_m &= \sqrt{2KI_D} = \sqrt{2(400)(10)}\ \mu\text{A/V} = 89.44\ \mu\text{A/V}. \end{aligned}$$ Hence $\boxed{g_{m1}=g_{m2}=89.4\ \mu\text{A/V}=0.0894\ \text{mA/V}}$ — a small number, as it must be for a 10 µA tail per side.
4. Impose full current switching and read off the differential input. Full switching means one device takes the entire tail current and the other is exactly at cut-off. Taking $I_1=I_{bias}$ and $I_2=0$: the conducting device now needs an overdrive $\sqrt{2I_{bias}/K}$, while the cut-off device sits at $v_{GS2}=V_{TH}$ with no overdrive at all. Since both sources share one node, the differential input is the difference of the two gate–source voltages, $$v_{ID}=v_{GS1}-v_{GS2}=\left(V_{TH}+\sqrt{\frac{2I_{bias}}{K}}\right)-V_{TH}=\sqrt{\frac{2\,(20\ \mu\text{A})}{400\ \mu\text{A/V}^2}}=\sqrt{0.1}=0.3162\ \text{V}.$$ Numerically $v_{GS1}=1.316$ V and $v_{GS2}=1.000$ V at that instant. Note the compact form: $\sqrt{2I_{bias}/K}=\sqrt{2}\,V_{ov}$, so $$\boxed{v_{ID}=\pm\sqrt{2}\,V_{ov}=\pm 0.316\ \text{V}}$$ the sign selecting which side captures the current. The pair is therefore linear only over a window of roughly $\pm 0.1$ V and is fully switched by about a third of a volt.
5. Part (b) — define the input offset produced by a load mismatch. The input offset voltage is the differential input that must be applied to bring the output back to zero when the circuit is not perfectly matched. With $R_{D1}=R_D+\tfrac12\Delta R_D$ and $R_{D2}=R_D-\tfrac12\Delta R_D$ and the inputs tied together, each drain carries $I_{bias}/2$, so the output error voltage is $$v_O = \frac{I_{bias}}{2}\,(R_{D2}-R_{D1}) = -\frac{I_{bias}}{2}\,\Delta R_D .$$
6. Refer that error back to the input. Dividing by the differential gain $A_d=g_m R_D$ and substituting $g_m = 2I_D/V_{ov} = I_{bias}/V_{ov}$ collapses the load resistance out of the problem entirely: $$V_{OS}=\frac{|v_O|}{A_d}=\frac{(I_{bias}/2)\Delta R_D}{g_m R_D}=\frac{V_{ov}}{2}\,\frac{\Delta R_D}{R_D}.$$ With a 2 per cent mismatch, $$\boxed{V_{OS}=\frac{0.2236\ \text{V}}{2}\times 0.02 = 2.24\ \text{mV}}$$ The result depends only on the overdrive and the fractional mismatch, which is why low-offset pairs are biased at small $V_{ov}$.
7. Part (c) — refer a threshold mismatch to the input. A threshold mismatch already lives in the gate–source loop, so it needs no gain to refer it: if $M_1$ and $M_2$ differ by $\Delta V_{TH}$, an equal and opposite differential input restores balance exactly. A 2 per cent mismatch on a 1 V threshold is $\Delta V_{TH}=0.02\times 1\ \text{V}=20$ mV, hence $$\boxed{V_{OS}=\Delta V_{TH}=20\ \text{mV}}$$ This term is nearly an order of magnitude larger than the resistor term of part (b), and it does not improve with bias current — threshold matching, not resistor matching, is what limits the offset of this pair.