Common-Source Amplifier — Mid-Band Gain and Design of the Coupling and Bypass Capacitors: 22-Elec-B5 Advanced Electronics, December 2019, Q2

Question 2: Common-Source Amplifier — Mid-Band Gain and Design of the Coupling and Bypass Capacitors (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Quantity	Symbol	Value
Supply	$V_{DD}$	20 V
Drain current, gate–source voltage, drain voltage	$I_D$, $V_{GS}$, $V_D$	1 mA, 2 V, +15 V
Bias divider	$R_{G1}$, $R_{G2}$	1.45 MΩ, 0.55 MΩ
Source and drain resistors	$R_S$, $R_D$	3.5 kΩ, 5 kΩ
Source resistance and load	$R_i$, $R_L$	100 kΩ, 10 kΩ
Device parameters	$V_{TH}$, $K$, $r_o$	1 V, 1 mA/V², infinite
Specified dominant low-frequency pole	$f_L$	100 Hz

Find. The mid-band voltage gain $v_o/v_i$, and values for $C_{C1}$, $C_{C2}$ and $C_S$ that put the dominant low-frequency pole at 100 Hz with every other pole and zero at least a decade below it.

Figure 2.1 — The common-source stage of Question 2. Three capacitors set the low-frequency response: $C_{C1}$ at the input, $C_{C2}$ at the output, and the bypass capacitor $C_S$ across $R_S$. Because $r_o$ is infinite and the device capacitances are ignored, each one contributes a single short-circuit time constant.

Approach. Confirm the bias point (it is over-specified, and the redundancy is the check), get $g_m$ from it, evaluate the mid-band gain with the gate divider included, then find the resistance seen by each capacitor with the other two shorted — the short-circuit time-constant method — and allocate the three poles so that exactly one sits at 100 Hz.

Confirm the quiescent point from the bias network. The gate divider draws negligible current, so $$V_G = V_{DD}\frac{R_{G2}}{R_{G1}+R_{G2}} = 20\times\frac{0.55}{2.00} = 5.5\ \text{V},$$ which places the source at $V_S = V_G - V_{GS} = 5.5-2 = 3.5$ V and therefore $I_D = V_S/R_S = 3.5/3.5\ \text{k}\Omega = 1.0$ mA. The drain then sits at $V_D = V_{DD}-I_D R_D = 20-5 = 15$ V, exactly as stated. Three independent routes agree, so the operating point is trustworthy; note also $V_{DS}=15-3.5=11.5\ \text{V} > V_{ov}$, confirming saturation.
Extract the transconductance. The overdrive is $V_{ov}=V_{GS}-V_{TH}=2-1=1$ V and, with the drain current fixed at 1 mA by the bias network, $$g_m = \frac{2I_D}{V_{ov}} = \frac{2\times 1\ \text{mA}}{1\ \text{V}} = 2\ \text{mA/V}.$$ $$\boxed{g_m = 2\ \text{mA/V}}$$
Check — which $K$ convention. The 1 mA drain current and the 1 V overdrive together require $I_D=K V_{ov}^2$ with $K=\tfrac12\mu C_{ox}(W/L)=1\ \text{mA/V}^2$, which is the convention used here. Under the half-factor convention printed on Question 1's formula sheet the same $K$ and $V_{ov}$ would give $I_D=0.5$ mA and $g_m=KV_{ov}=1$ mA/V, contradicting the bias network in three places. The bias data governs; $g_m=2I_D/V_{ov}=2$ mA/V is convention-free and is the value carried forward. A solution built on $g_m=1$ mA/V would halve every gain below.
Compute the mid-band gain. In the mid-band all three capacitors are short circuits, so the source is fully bypassed, the drain sees $R_D\parallel R_L$, and the signal source is attenuated by the divider formed by $R_i$ and the parallel bias resistors $R_G=R_{G1}\parallel R_{G2}$: $$R_G = \frac{1.45\times 0.55}{1.45+0.55}\ \text{M}\Omega = 0.39875\ \text{M}\Omega = 398.75\ \text{k}\Omega ,$$ $$R_D\parallel R_L = \frac{5\times 10}{5+10}\ \text{k}\Omega = 3.333\ \text{k}\Omega .$$ Because $R_{in}=R_G$ with the gate drawing no current, the gain from the source to the output is $$A_M=\frac{v_o}{v_i}=-g_m(R_D\parallel R_L)\frac{R_G}{R_G+R_i}=-2\times 3.333\times\frac{398.75}{498.75},$$ $$\boxed{A_M = -5.33\ \text{V/V}\quad(14.5\ \text{dB})}$$ The divider costs 20 per cent of the gain, which is the price of a 100 kΩ source driving a 399 kΩ bias network.
Find the resistance each capacitor sees. Applying the short-circuit time-constant method — look into the capacitor's terminals with the other two shorted — and remembering that $r_o=\infty$: $$\begin{aligned} R_{C1} &= R_i + (R_{G1}\parallel R_{G2}) = 100 + 398.75 = 498.75\ \text{k}\Omega,\\ R_{C2} &= R_D + R_L = 5 + 10 = 15\ \text{k}\Omega,\\ R_{CS} &= R_S\parallel\frac{1}{g_m} = 3.5\ \text{k}\Omega\parallel 0.5\ \text{k}\Omega = 437.5\ \Omega . \end{aligned}$$ The bypass capacitor sees by far the smallest resistance — looking into the source terminal of the transistor is looking into $1/g_m$ — so it will need by far the largest capacitance.
Establish why $C_S$ cannot own the dominant pole. The source network contributes not only a pole at $1/(2\pi R_{CS}C_S)$ but also a zero at $1/(2\pi R_S C_S)$, where the bypass capacitor stops shorting $R_S$. Their ratio is fixed by the circuit and not by the capacitor value: $$\frac{f_{p,S}}{f_{z,S}}=\frac{R_S}{R_S\parallel(1/g_m)}=1+g_m R_S = 1+2\times 3.5 = 8 .$$ Eight is less than ten, so if the $C_S$ pole were placed at 100 Hz its own zero would land at 12.5 Hz — inside the one-decade exclusion the question demands. The dominant pole must therefore be supplied by one of the coupling capacitors, and the source network pushed a decade down. This is the point of the question.
Allocate the poles and size the capacitors. Put the dominant pole on $C_{C1}$, which sees the largest resistance and so buys 100 Hz for the least capacitance, and place the remaining pole and the whole source pole–zero pair at 10 Hz or below: $$\begin{aligned} C_{C1} &= \frac{1}{2\pi R_{C1}f_L} = \frac{1}{2\pi (498.75\ \text{k}\Omega)(100\ \text{Hz})} = 3.19\ \text{nF},\\ C_{C2} &= \frac{1}{2\pi R_{C2}(f_L/10)} = \frac{1}{2\pi (15\ \text{k}\Omega)(10\ \text{Hz})} = 1.06\ \mu\text{F},\\ C_S &= \frac{1}{2\pi R_{CS}(f_L/10)} = \frac{1}{2\pi (437.5\ \Omega)(10\ \text{Hz})} = 36.4\ \mu\text{F}. \end{aligned}$$ $$\boxed{C_{C1}=3.19\ \text{nF},\quad C_{C2}=1.06\ \mu\text{F},\quad C_S=36.4\ \mu\text{F}}$$ The associated source zero then falls at $1/(2\pi R_S C_S)=1.25$ Hz, and the pole map reads 100 Hz (dominant), 10 Hz, 10 Hz, and a zero at 1.25 Hz — every one of them at least a decade from the dominant pole, as specified.
Round to standard values and check the realised corner. Rounding the two subordinate capacitors up keeps their poles below 10 Hz, while rounding the dominant capacitor up only lowers the corner, which is the safe direction: E12 values $C_{C1}=3.3$ nF, $C_{C2}=1.2\ \mu$F and $C_S=39\ \mu$F give poles at 96.7 Hz, 8.84 Hz and 9.33 Hz with the zero at 1.17 Hz. Evaluating the exact transfer function $$A(s)=A_M\left(\frac{s}{s+\omega_1}\right)\left(\frac{s}{s+\omega_2}\right)\left(\frac{s+\omega_z}{s+\omega_p}\right)$$ and solving $|A|=|A_M|/\sqrt2$ gives a true −3 dB frequency of 98.4 Hz with the standard values (101.9 Hz with the exact values above). The agreement confirms that the dominant-pole assumption is sound: the subordinate poles shift the corner by only about 2 per cent.

Quantity	Symbol	Result
Bias check (gate, source, drain)	$V_G$, $V_S$, $V_D$	5.5 V, 3.5 V, 15 V
Transconductance	$g_m$	2 mA/V
Parallel bias resistance	$R_G$	398.75 kΩ
Mid-band gain	$A_M=v_o/v_i$	−5.33 V/V (14.5 dB)
Resistance seen by $C_{C1}$, $C_{C2}$, $C_S$	$R_{C1}$, $R_{C2}$, $R_{CS}$	498.75 kΩ, 15 kΩ, 437.5 Ω
Input coupling capacitor (dominant pole, 100 Hz)	$C_{C1}$	3.19 nF (use 3.3 nF)
Output coupling capacitor (pole at 10 Hz)	$C_{C2}$	1.06 µF (use 1.2 µF)
Source bypass capacitor (pole at 10 Hz)	$C_S$	36.4 µF (use 39 µF)
Source-network zero	$f_{z,S}$	1.25 Hz
Exact −3 dB corner (standard values)	$f_L$	98.4 Hz

Topic. Low-frequency response of a capacitively coupled common-source amplifier, and the design of coupling and bypass capacitors by the short-circuit time-constant method.

Key relations. Mid-band gain $A_M=-g_m(R_D\parallel R_L)\,R_G/(R_G+R_i)$; short-circuit time constants $R_{C1}=R_i+R_G$, $R_{C2}=R_D+R_L$, $R_{CS}=R_S\parallel(1/g_m)$; pole $f=1/(2\pi RC)$; source-network zero $f_z=1/(2\pi R_S C_S)$ with the fixed ratio $f_p/f_z=1+g_m R_S$; estimate $f_L\approx\sum 1/(2\pi R_iC_i)$.

Why this works. Each capacitor is a high-pass element in series with a resistance the rest of the circuit presents to it, so at frequencies well above its own corner it is a short and contributes nothing. Shorting the other capacitors while evaluating one of them is legitimate precisely because the poles are well separated by design, which is the condition the question imposes. The bypass capacitor is different in kind: it does not merely couple, it removes degeneration, and when it stops shorting $R_S$ the gain falls to the degenerated value rather than to zero. That surviving gain is what creates the zero, and the ratio between the pole and the zero is exactly the degeneration factor $1+g_mR_S$ — a property of the bias design, immune to the capacitor value. Recognising that the specification (one decade) exceeds what the circuit can deliver (a factor of eight) is the design insight the marks are hiding behind.

Common pitfall. Assigning the dominant pole to $C_S$ by reflex because it sees the smallest resistance, and then never checking its zero — the resulting design violates the stated one-decade separation and lets the response start rolling off above 12 Hz. A second pitfall is forgetting the $R_G/(R_G+R_i)$ divider and quoting $-g_m(R_D\parallel R_L)=-6.67$ V/V; with a 100 kΩ source that is 25 per cent optimistic.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §10.1 (low-frequency response of the CS and CE amplifiers) and §7.3 (biasing); Gray, Hurst, Lewis & Meyer, 5th ed., §7.3 (short-circuit time constants).

Question 2 of 5: Common-Source Amplifier — Mid-Band Gain and Design of the Coupling and Bypass Capacitors

Question 2: Common-Source Amplifier — Mid-Band Gain and Design of the Coupling and Bypass Capacitors (20 marks)