Question 4 of 5: Op-Amp with a Diode-Connected Transistor in the Feedback Path — A Logarithmic Amplifier
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, December 2019 — 16-Elec-B5
Advanced Electronics. Three hours; CLOSED BOOK, an approved Casio or Sharp
calculator permitted. Five questions, ALL to be answered, 20 marks each. Op-amps are
ideal and the supplies are ±15 V unless a question states otherwise; in
schematics ground and chassis are common. Where a question leaves an interpretation
open, the paper's own Note 1 invites the candidate to state the assumption inside the
answer — every such assumption below is flagged in a check callout.
Reference texts. A. S. Sedra and K. C. Smith, Microelectronic
Circuits, 8th ed. — Ch. 7 (transistor amplifiers and biasing), Ch. 8
(differential and multistage amplifiers, offset voltage), Ch. 10 (frequency response,
short-circuit time constants), Ch. 11 (output stages and power amplifiers), Ch. 12
(feedback topologies). B. Razavi, Fundamentals of Microelectronics, 2nd ed.,
Ch. 8 (operational amplifier as a black box, non-linear feedback elements) and
Ch. 10 (differential amplifiers). P. Gray, P. Hurst, S. Lewis and R. Meyer,
Analysis and Design of Analog Integrated Circuits, 5th ed., Ch. 3
(single-transistor amplifiers) and Ch. 8 (feedback).
Check — the paper's own MOSFET convention.
The formula sheet printed with Question 1 defines the saturation current as
$i_{DS}=\tfrac12 K\,(v_{GS}-V_{TH})^2$ with $K=K'(W/L)=\mu C_{ox}(W/L)$, and that
convention is used throughout Questions 1 and 5. Question 2 is the one place where it
does not close: with $K=1\ \text{mA/V}^2$ and $V_{GS}=2$ V the sheet would give
$I_D=0.5$ mA, whereas the bias network of Question 2 fixes $I_D=1$ mA by three
independent routes (the gate divider, $V_S/R_S$, and the stated $V_D$). The bias data
therefore governs there, and the transconductance is taken as $g_m=2I_D/V_{ov}$,
which is convention-free. Both readings are quoted in Question 2, Step 2.
Question 4: Op-Amp with a Diode-Connected Transistor in the Feedback Path — A Logarithmic Amplifier (20 marks)
Given. An ideal op-amp $A_1$ (infinite gain and input resistance,
zero input current, output saturating at the ±15 V rails specified in the paper's
Note 7). The input source $v_{IN}$ drives the non-inverting terminal directly. The
inverting terminal sits on node $v_x$, which is returned to ground through $R_1$ and
connected to the base and collector of the pnp transistor $Q_1$; the emitter of
$Q_1$ is the op-amp output node $v_{OUT}$. $Q_1$ is therefore diode-connected, with the
emitter–base junction bridging output to summing node. Transistor parameters:
saturation current $I_S$, common-emitter current gain $\beta$, thermal voltage
$V_T = kT/q \approx 25$ mV at room temperature.
Find. The closed-form relationship $v_{OUT}(v_{IN})$, treating positive
and negative inputs separately as the question directs.
Figure 4.1 — The circuit of Question 4 as drawn on the paper. $Q_1$ is diode-connected: its base and collector are both tied to the summing node $v_x$, and its emitter is the op-amp output. $R_1$ returns $v_x$ to ground, so the input voltage — impressed on $v_x$ through the virtual short — sets the current that the junction must carry.
Approach. Use the virtual short to put $v_{IN}$ on the summing
node, read the current $R_1$ then demands, force the diode-connected transistor to carry it,
and invert the exponential junction law to get $v_{OUT}$. Then check the sign of the loop
and repeat the argument for a negative input, where the junction cannot conduct and the
feedback path disappears.
Positive inputs — place the summing node. The op-amp is ideal and,
as Step 5 confirms, the loop is negative for $v_{IN}>0$, so the two input terminals are held
at the same potential:
$$v_x = v_{IN}.$$
No current enters the inverting terminal, so every ampere that flows down $R_1$ must arrive
from the transistor.
Read the current the resistor demands. With $v_x$ pinned at $v_{IN}$ and
the far end of $R_1$ grounded,
$$I_{R1} = \frac{v_x}{R_1} = \frac{v_{IN}}{R_1},$$
directed from the summing node down through $R_1$ to ground. This current is supplied by the
emitter of $Q_1$, entering the node through the shorted base–collector pair, so
$I_E = v_{IN}/R_1$. The circuit has thus converted the input voltage into a precisely known
junction current — the first half of the logarithmic conversion.
Impose the exponential junction law. With base and collector shorted the
device is always at $V_{CB}=0$ and therefore always in the active region for any forward
bias, so no region checking is needed anywhere in the range. The collector current obeys
$$\begin{aligned}
I_C &= I_S\exp\!\left(\frac{V_{EB}}{V_T}\right),\\
I_E &= I_C\,\frac{\beta+1}{\beta} = \frac{I_C}{\alpha},
\end{aligned}$$
where $V_{EB}=v_{OUT}-v_x$ is the emitter–base forward bias, since the emitter is at
the output and the base at $v_x$.
Invert the exponential and assemble the transfer relation. Substituting
$I_C=\alpha I_E = \alpha\,v_{IN}/R_1$ and solving for the junction voltage,
$$V_{EB} = V_T\ln\!\left(\frac{I_C}{I_S}\right) = V_T\ln\!\left(\frac{\alpha\,v_{IN}}{I_S R_1}\right),$$
and because $v_{OUT}=v_x+V_{EB}=v_{IN}+V_{EB}$,
$$\boxed{v_{OUT} = v_{IN} + V_T\ln\!\left(\frac{\alpha\,v_{IN}}{I_S R_1}\right),\quad \alpha=\frac{\beta}{\beta+1},\ v_{IN}>0}$$
For any practical $\beta$ the factor $\alpha=\beta/(\beta+1)$ is within a couple of per cent
of unity and the compact engineering form
$v_{OUT}\simeq v_{IN}+V_T\ln\!\left(v_{IN}/(I_SR_1)\right)$ is used. The dominant term is
logarithmic: the output moves by only $V_T\ln 10 = 57.6$ mV per decade of input.
Confirm the loop polarity, which is what makes the derivation legal.
Perturb the output upward: $V_{EB}=v_{OUT}-v_x$ increases, the junction current rises
exponentially, more current is pushed into $v_x$, so $v_x$ rises — and $v_x$ drives the
inverting terminal, so the op-amp output falls. The perturbation is opposed, the
feedback is negative, and the virtual short assumed in Step 1 is justified.
Negative inputs — the feedback path opens. A negative $v_{IN}$
would require the current in $R_1$ to flow up into the summing node, i.e. out of the
node into the transistor. The emitter–base junction cannot conduct in that direction,
so $Q_1$ cuts off. The summing node is then connected to nothing but $R_1$ and the (currentless)
inverting terminal, so it is pulled to ground, $v_x = 0$. The op-amp now sees a permanently
negative differential input $v_{IN}-v_x = v_{IN} < 0$ and drives its output hard to the
negative rail:
$$\boxed{v_{OUT} = -V_{SAT} \simeq -15\ \text{V},\qquad v_{IN}\le 0}$$
The state is self-consistent: with $v_{OUT}=-15$ V the junction bias is
$V_{EB}=-15$ V, firmly reverse-biased, so $Q_1$ stays off and the circuit does not latch back.
This one-sided behaviour is exactly what the question's warning points at — the block
is a logarithmic converter for positive inputs and a saturated comparator for negative ones.
Put numbers on it, and state the useful range. Taking representative
values $R_1 = 10\ \text{k}\Omega$, $I_S = 10^{-14}$ A, $\beta = 50$ and $V_T = 25$ mV: an
input of 1 V gives $I_E = 100\ \mu$A, $I_C = 98.04\ \mu$A, $V_{EB} = 575.2$ mV and
$v_{OUT} = 1.575$ V; an input of 0.1 V gives $I_E = 10\ \mu$A, $I_C = 9.804\ \mu$A,
$V_{EB} = 517.6$ mV and $v_{OUT} = 0.618$ V. A tenfold change of input has moved the
logarithmic term by 57.6 mV, as predicted. The upper limit is the op-amp rail
($v_{IN}+V_{EB}\le 15$ V), and the lower limit is set by the op-amp input offset and the
transistor's leakage, which corrupt the logarithm once $v_{IN}/R_1$ approaches the
nanoampere range — three to five usable decades in practice.
