0.18 µm CMOS Differential Pair — Device Sizing and Differential Gain: 22-Elec-B5 Advanced Electronics, Undated paper, Q3

Question 3: 0.18 µm CMOS Differential Pair — Device Sizing and Differential Gain (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Quantity	Symbol	Value
Supply rails	$V_{DD} = \|V_{SS}\|$	1.5 V
Threshold magnitude, all devices	$\|V_{TH}\|$	0.5 V
Channel length, all devices	$L$	0.36 µm
NMOS transconductance parameter	$\mu_n C_{ox}$	400 µA/V$^2$
PMOS transconductance parameter	$\mu_p C_{ox}$	400/4 = 100 µA/V$^2$
Channel-length modulation	$\lambda$	0.2 V$^{-1}$
Tail current	$I_{bias}$	200 µA
Overdrive, all devices	$\|V_{ov}\|$	0.2 V

Find. (a) the aspect ratios $(W/L)_{1..4}$ that put all four transistors at $|V_{ov}| = 0.2$ V while carrying their share of the tail current, and (b) the small-signal differential voltage gain $A_d = v_{do}/v_{id}$ of the resulting design.

The circuit as drawn on the paper: an NMOS pair M₁/M₂ on a tail source I_bias returning to −V_SS, PMOS loads M₃/M₄ whose gates are tied together to the bias node V_G1, and the output v_do taken differentially between the two drains — note the minus sign on the M₁ drain and the plus on the M₂ drain.

Approach. Split the tail current between the two branches, invert the square law once per device type to get the sizes, then evaluate the differential half circuit as $g_m$ working into the parallel combination of the two output resistances.

Part (a) — fix the current every device must carry. The pair is balanced when $v_{id} = 0$, so the tail splits evenly and the two PMOS loads must pass exactly the same current as the devices below them: $$I_{D1}=I_{D2}=I_{D3}=I_{D4}=\frac{I_{bias}}{2}=\frac{200\ \mu\text{A}}{2}=100\ \mu\text{A}$$ Every subsequent sizing calculation is this one current pushed through the square law at the specified overdrive.
Size the NMOS input pair from the saturation equation. Neglecting $\lambda v_{DS}$ for sizing purposes (it perturbs the current by a few per cent and is restored in part (b)), $I_D = \tfrac12\,\mu_n C_{ox}\,(W/L)\,V_{ov}^2$, so $$\left(\frac{W}{L}\right)_{1,2}=\frac{2I_D}{\mu_n C_{ox}V_{ov}^2} =\frac{2(100\times10^{-6})}{(400\times10^{-6})(0.2)^2} =\frac{200\times10^{-6}}{16\times10^{-6}}$$ which evaluates to $\boxed{(W/L)_{1}=(W/L)_{2}=12.5}$. At the stated $L = 0.36$ µm that is a drawn width $W_1 = W_2 = 12.5 \times 0.36 = 4.5$ µm.
Size the PMOS loads with the mobility-corrected parameter. The paper writes $\mu_n C_{ox} = 4\mu_p C_{ox} = 400$ µA/V$^2$, so the PMOS parameter is $\mu_p C_{ox} = 100$ µA/V$^2$ — holes are four times less mobile than electrons. Repeating the same inversion at the same current and the same overdrive magnitude, $$\left(\frac{W}{L}\right)_{3,4}=\frac{2I_D}{\mu_p C_{ox}V_{ov}^2} =\frac{2(100\times10^{-6})}{(100\times10^{-6})(0.2)^2}=\frac{200}{4}$$ giving $\boxed{(W/L)_{3}=(W/L)_{4}=50}$, i.e. $W_3 = W_4 = 18$ µm.
Use the mobility ratio as a free check on the sizing. Since all four devices carry the same current at the same overdrive magnitude, the ratio of the PMOS to the NMOS aspect ratio must come out as exactly the mobility ratio: $50/12.5 = 4 = \mu_n C_{ox}/\mu_p C_{ox}$. That check costs nothing and catches an arithmetic slip in either sizing immediately.
Confirm the bias point fits between the rails. Each input device needs $V_{GS} = V_{TH} + V_{ov} = 0.5 + 0.2 = 0.7$ V, and each PMOS load needs $|V_{SG}| = 0.7$ V, so its gate bias sits at $V_{G1} = V_{DD} - |V_{TH}| - |V_{ov}| = 1.5 - 0.7 = 0.8$ V. With 1.5 V rails there is room for the tail source and for both devices to stay saturated, so the design is physically realisable and not merely arithmetically consistent.
Part (b) — evaluate the two small-signal parameters. At the designed operating point, $$\begin{aligned} g_m &= \frac{2I_D}{V_{ov}} = \frac{2(100\times10^{-6})}{0.2} = 1.0\ \text{mA/V} \\[2pt] r_o &= \frac{1}{\lambda I_D} = \frac{1}{(0.2)(100\times10^{-6})} = 50\ \text{k}\Omega \end{aligned}$$ Both output resistances are equal here because the loads carry the same current with the same $\lambda$, so $r_{o1} = r_{o2} = r_{o3} = r_{o4} = 50$ k$\Omega$. The intrinsic gain of a single device is $g_m r_o = 50$.
Assemble the differential gain from the half circuit. The output is taken differentially between the two drains, so each half circuit is a common-source stage whose load is the parallel combination of the NMOS and PMOS output resistances at that drain: $$A_d = \frac{v_{do}}{v_{id}} = g_m\left(r_{oN}\parallel r_{oP}\right) = (1.0\times10^{-3})\left(\frac{50\times50}{50+50}\times10^{3}\right) = (1.0\times10^{-3})(25\times10^{3})$$ which gives $\boxed{A_d = 25\ \text{V/V} \equiv 27.96\ \text{dB}}$.
Collapse the result to a form that is worth remembering. Because the load devices share the pair’s $\lambda$ and $I_D$, everything except the Early voltage and the overdrive cancels: $$A_d = g_m\frac{r_o}{2} = \frac{2I_D}{V_{ov}}\cdot\frac{1}{2\lambda I_D} = \frac{1}{\lambda V_{ov}} = \frac{V_A}{V_{ov}} = \frac{5}{0.2} = 25$$ exactly half the intrinsic gain, and independent of the bias current. This is the real lesson of the question: in a current-mirror-loaded pair, spending more current buys bandwidth, not gain — only a longer channel or a lower overdrive raises $A_d$.

Check: how $\lambda = 0.2$ should be read. The paper’s own formula sheet prints both $V_A = 1/\lambda$ and $V_A = V_A'L$, and it gives $L$, so the stated “$\lambda = 0.2$” admits two readings. Taken literally as a V$^{-1}$ coefficient it gives $V_A = 5$ V, $r_o = 1/(\lambda I_D) = 50$ k$\Omega$ and $A_d = 25$ — the reading used above, and the only one consistent with the sheet’s own $r_o = 1/(\lambda I_D)$. Read instead as a per-micron $\lambda'$, it would give $V_A = V_A'L = (1/0.2)(0.36) = 1.8$ V, $r_o = 18$ k$\Omega$ and $A_d = 9$ — a factor of 2.8 lower. The boxed answer follows the literal reading; a candidate who states the assumption explicitly would be credited under Note 1 of the paper either way.

Quantity	Result
Branch current $I_D$	100 µA
(a) $(W/L)_1 = (W/L)_2$ — NMOS input pair	12.5 ($W = 4.5$ µm at $L = 0.36$ µm)
(a) $(W/L)_3 = (W/L)_4$ — PMOS loads	50 ($W = 18$ µm at $L = 0.36$ µm)
Gate–source voltages	$V_{GS1,2} = 0.7$ V; PMOS gate bias $V_{G1} = 0.8$ V
Transconductance, all devices	$g_m = 1.0$ mA/V
Output resistance, all devices	$r_o = 50$ k$\Omega$ ($V_A = 5$ V)
(b) Differential gain $A_d = v_{do}/v_{id}$	25 V/V (27.96 dB)
(b) Alternative reading $V_A = V_A'L = 1.8$ V	$A_d = 9$ V/V — see the check callout

Topic. Sizing a CMOS differential pair from a specified overdrive, and the differential half circuit.

Key relations. $I_D = \tfrac12\mu C_{ox}(W/L)V_{ov}^2$; $g_m = 2I_D/V_{ov} = \sqrt{2\mu C_{ox}(W/L)I_D}$; $r_o = 1/(\lambda I_D) = V_A/I_D$; differential gain $A_d = g_m\left(r_{oN}\parallel r_{oP}\right)$; the collapsed form $A_d = V_A/V_{ov}$, independent of bias current.

Why this works. Specifying the overdrive rather than the width is how analogue CMOS design is actually posed, because $V_{ov}$ is what sets speed, headroom and matching, while $W/L$ is only the consequence. Once $I_D$ and $V_{ov}$ are fixed the square law has exactly one unknown left, so each device size falls out in a single line. The gain then separates cleanly: $g_m$ is set by the bias point and the load resistance by $\lambda$, and because the load devices here carry the same current with the same $\lambda$, everything except $V_A$ and $V_{ov}$ cancels. A designer who wants more gain from one stage must lengthen the channel, which raises $V_A$, or lower the overdrive, which costs speed — adding current changes neither.

Common pitfall. Three recur here. Forgetting that $\mu_n C_{ox} = 4\mu_p C_{ox}$ and sizing the PMOS loads with the NMOS parameter, which makes them four times too narrow and silently moves them out of the intended operating point. Putting the full $I_{bias}$ through each input device instead of half of it, doubling every aspect ratio. And using $r_o$ alone as the load resistance in the gain expression when the drain node is loaded by two devices in parallel, which overstates $A_d$ by a factor of two.

Source. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., Section 4.4 (differential pair with current-mirror or current-source loads) and Section 2.4 (channel-length modulation, $V_A$ and $r_o$); Sedra & Smith, Microelectronic Circuits, 8th ed., Sections 8.2 and 8.5 (the differential half circuit and the active-loaded MOS differential pair).

Question 3 of 5: 0.18 µm CMOS Differential Pair — Device Sizing and Differential Gain

Question 3: 0.18 µm CMOS Differential Pair — Device Sizing and Differential Gain (20 marks)