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22-Elec-B5 Advanced Electronics · Undated paper

Question 5 of 5: Common-Emitter Amplifier — Sizing the Coupling and Bypass Capacitors for a 100 Hz Corner

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams May 2019, 16-Elec-B5 Advanced Electronics — 3 hours, CLOSED BOOK, one approved Casio or Sharp calculator. Five questions, all to be answered, 20 marks each (100 marks total). In schematics ground and chassis are common; op-amps are ideal and supply rails are ±15 V unless stated otherwise. Candidates are told to state any interpretive assumption inside the answer, and to supply block diagrams and schematics wherever an essay-format response needs them.

Reference texts. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. (Ch. 7 transistor amplifiers, Ch. 8 differential and multistage amplifiers, Ch. 10 frequency response, Ch. 11 feedback, Ch. 12 output stages and power amplifiers); B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. (Ch. 2 MOS device models, Ch. 4 differential amplifiers, Ch. 5 current mirrors) and Fundamentals of Microelectronics, 2nd ed.; R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, 5th ed. (Ch. 17 low-frequency response); P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. (Ch. 4 current mirrors, Ch. 8 feedback); R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 4th ed. (Ch. 20 current mirrors); Analog Devices, Data Conversion Handbook, W. Kester (ed.), Ch. 2 (quantisation).

How each answer is laid out. Every question states its data, the quantity sought, the circuit as drawn on the paper, a one-line strategy, then numbered steps carrying the governing relation, the substitution and the intermediate result. Boxed values are the answers a marker looks for, and each question closes with a results table and a concept note.

Question 5: Common-Emitter Amplifier — Sizing the Coupling and Bypass Capacitors for a 100 Hz Corner (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

QuantitySymbolValue
Upper bias resistor$R_{B1}$180 k$\Omega$
Lower bias resistor$R_{B2}$270 k$\Omega$
Source resistance$R_S$5 k$\Omega$
Collector resistor$R_C$8 k$\Omega$
Emitter resistor$R_E$2 k$\Omega$
Load resistor$R_L$5 k$\Omega$
Current gain$\beta$100
Transconductance$g_m$40 mA/V
Input resistance of the base$r_{\pi}$2.5 k$\Omega$
Target lower cutoff$f_L$100 Hz

Find. Values for the two coupling capacitors and the emitter bypass capacitor that place the −3 dB corner of the amplifier at 100 Hz, together with a statement of which one actually sets that corner.

+VCCRB1RB2RCvsRSCC1Q1RECECC2RLvo
The amplifier as drawn on the paper. CC1 couples the source into the base, CC2 couples the collector into the load, and CE bypasses the emitter resistor. All three are open circuits at d.c. and short circuits in the mid-band, so each contributes one high-pass pole at the bottom of the passband.

Approach. Use the method of short-circuit time constants: with all the other capacitors shorted, find the resistance each capacitor sees, sum the three reciprocal time constants to get $\omega_L$, and allocate that budget deliberately rather than splitting it evenly.

  1. Confirm the small-signal data is self-consistent before using it. The paper gives $\beta$, $g_m$ and $r_{\pi}$ independently, and they must satisfy $\beta = g_m r_{\pi}$: $$g_m r_{\pi} = (40\times10^{-3})(2500) = 100 = \beta \ \checkmark$$ They also imply a quiescent collector current $I_C = g_m V_T = (40\ \text{mA/V})(25\ \text{mV}) = 1$ mA, a thoroughly ordinary bias point, so the “already biased properly” premise is credible and no d.c. analysis is needed.
  2. Set up the method that makes this a three-line problem. Each capacitor contributes one high-pass pole. In the short-circuit time-constant method the pole frequencies add: $$\omega_L \approx \sum_i \frac{1}{R_i C_i} = \frac{1}{R_{C1}C_{C1}} + \frac{1}{R_{C2}C_{C2}} + \frac{1}{R_{E}'C_{E}}$$ where $R_i$ is the resistance seen by capacitor $i$ with every other capacitor replaced by a short. The target is $\omega_L = 2\pi f_L = 2\pi(100) = 628.3$ rad/s.
  3. Find the resistance seen by the input coupling capacitor. With $C_E$ shorted the emitter is at a.c. ground, so the base looks into $r_{\pi}$ alone, in parallel with the bias network; the capacitor sees that in series with the source: $$\begin{aligned} R_B &= R_{B1}\parallel R_{B2} = 180\parallel 270 = 108\ \text{k}\Omega \\[2pt] R_{C1} &= R_S + \left(R_B \parallel r_{\pi}\right) = 5000 + 2443 = 7443\ \Omega \end{aligned}$$ The 108 k$\Omega$ bias network barely matters here, because $r_{\pi}$ is forty times smaller and dominates the parallel combination.
  4. Find the resistance seen by the output coupling capacitor. Looking out from $C_{C2}$ in both directions, the collector node presents $R_C$ in series with the load (the transistor’s own $r_o$ is not given and is neglected): $$R_{C2} = R_C + R_L = 8 + 5 = 13\ \text{k}\Omega$$ This is the largest of the three resistances, which is why $C_{C2}$ will turn out to be the smallest capacitor.
  5. Find the resistance seen by the bypass capacitor, which is the crucial one. Looking up into the emitter with both coupling capacitors shorted, the base circuit is divided by $(\beta+1)$, and that appears in parallel with $R_E$: $$R_E' = R_E \parallel \frac{r_{\pi} + \left(R_S\parallel R_B\right)}{\beta+1} = 2000 \parallel \frac{2500 + 4779}{101} = 2000 \parallel 72.07$$ which evaluates to $R_E' = 69.6\ \Omega$. This is two orders of magnitude smaller than the other two resistances, and that single fact decides the whole design.
  6. Allocate the frequency budget instead of splitting it evenly. Good practice is to let one capacitor set the corner and push the other two a decade below, so that the response has a clean single-pole roll-off near $f_L$ rather than three poles piled up together. Since $R_E'$ is by far the smallest resistance, $C_E$ is the capacitor that must be large anyway, so it is the natural choice to carry the corner: $$f_{C1} = f_{C2} = \frac{f_L}{10} = 10\ \text{Hz} \qquad\Longrightarrow\qquad f_{CE} = f_L - f_{C1} - f_{C2} = 100 - 10 - 10 = 80\ \text{Hz}$$ so $C_E$ carries 80 percent of the total budget.
  7. Size the two coupling capacitors. Applying $C = 1/(2\pi f R)$ to each, $$\begin{aligned} C_{C1} &= \frac{1}{2\pi(10)(7443)} = 2.14\ \mu\text{F} \\[2pt] C_{C2} &= \frac{1}{2\pi(10)(13000)} = 1.22\ \mu\text{F} \end{aligned}$$ so $\boxed{C_{C1} = 2.14\ \mu\text{F},\quad C_{C2} = 1.22\ \mu\text{F}}$.
  8. Size the bypass capacitor against the small emitter resistance. The same formula at the 80 Hz share and the 69.6 $\Omega$ driving-point resistance gives $$C_E = \frac{1}{2\pi(80)(69.56)} = 2.86\times10^{-5}\ \text{F}$$ that is, $\boxed{C_E = 28.6\ \mu\text{F}}$ — more than twenty times either coupling capacitor, exactly as the resistance ratio predicts.
  9. Answer the second half of the question explicitly. $\boxed{C_E\ \text{dominates the corner frequency}}$. Its pole sits at 80 Hz against 10 Hz for each coupling capacitor, so it supplies 80 percent of $\omega_L$; and the reason is structural rather than a consequence of the allocation chosen, because the emitter node is the low-impedance point of the circuit — the base resistance seen there is divided by $(\beta+1)$ — so any bypass capacitor of a reasonable size has a much higher corner than a coupling capacitor of the same value would.
  10. Verify the design against the full network, and then round to stock values. Solving the complete four-node circuit with these three capacitors places the exact −3 dB point at 90.1 Hz, safely below the 100 Hz specification — the time-constant sum is an upper bound on $f_L$, so it errs on the conservative side, which is what a specification of this form wants. Rounding to the nearest E12 values, $C_{C1} = 2.2\ \mu$F, $C_{C2} = 1.2\ \mu$F and $C_E = 33\ \mu$F, gives a computed corner of 89.3 Hz, still inside specification. For reference, the mid-band gain of the stage is $$|A_v| = g_m\left(R_C\parallel R_L\right) \frac{R_B\parallel r_{\pi}}{R_S + \left(R_B\parallel r_{\pi}\right)} = (40\times10^{-3})(3077)\frac{2443}{7443} = 40.4$$ or 32.1 dB, which the full nodal solve reproduces exactly.
QuantityResult
Bias network $R_B = R_{B1}\parallel R_{B2}$108 k$\Omega$
Resistance seen by $C_{C1}$$R_S + (R_B\parallel r_{\pi}) = 7.44$ k$\Omega$
Resistance seen by $C_{C2}$$R_C + R_L = 13$ k$\Omega$
Resistance seen by $C_E$$R_E \parallel \left[(r_{\pi}+R_S\parallel R_B)/(\beta+1)\right] = 69.6\ \Omega$
Pole allocation$f_{C1} = f_{C2} = 10$ Hz, $f_{CE} = 80$ Hz (sum = 100 Hz)
Input coupling capacitor $C_{C1}$2.14 µF  (E12: 2.2 µF)
Output coupling capacitor $C_{C2}$1.22 µF  (E12: 1.2 µF)
Emitter bypass capacitor $C_E$28.6 µF  (E12: 33 µF)
Dominant capacitor$C_E$ — 80 percent of $\omega_L$
Exact −3 dB point of the design90.1 Hz (89.3 Hz with E12 values)
Mid-band gain40.4 V/V (32.1 dB)
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