CMOS Current-Source Bias Generator — Sizing, Ratioing and Compliance: 22-Elec-B5 Advanced Electronics, Undated paper, Q4

Question 4: CMOS Current-Source Bias Generator — Sizing, Ratioing and Compliance (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Quantity	Symbol	Value
Supply	$V_{DD}$	3.0 V
Threshold magnitude, all devices	$\|V_{TH}\|$	0.5 V
Channel length of the p-channel devices	$L_p$	0.36 µm
NMOS transconductance parameter	$\mu_n C_{ox}$	400 µA/V$^2$
PMOS transconductance parameter	$\mu_p C_{ox}$	400/4 = 100 µA/V$^2$
Channel-length modulation	$\lambda$	0.2 V$^{-1}$
Reference current in the diode stack	$I_{bias}$	200 µA
Overdrive of every p-channel device	$\|V_{ov}\|$	0.3 V
Output-current specification	$I_3 = 4I_4 = 8I_{bias}$	$I_3 = 1.6$ mA, $I_4 = 400$ µA
Compliance swing to be examined	$V_3$	0 to 1.5 V

Find. (a) the aspect ratios of the two devices in the reference branch, (b) the aspect ratios of the two output devices that realise the specified current ratios, and (c) how much $I_3$ actually moves as its load node is swept over 1.5 V.

The bias generator as drawn on the paper. The reference branch is a CMOS diode stack: PMOS M₂ with its source at +V_DD sits in series with NMOS M₁ with its source at ground, and one wire ties both gates to their common drain node. That node sets the gate voltage of the PMOS current sources M₃ and M₄, which deliver I₃ and I₄ into loads held at V₃ and V₄.

Approach. Size the diode-connected PMOS from its stated overdrive, let the supply headroom that is left over fix the NMOS overdrive, scale the output devices by their current ratios, and then let channel-length modulation alone account for the variation of $I_3$ with its drain voltage.

Part (a) — size the diode-connected PMOS from the stated overdrive. $M_2$ carries the whole reference current at the specified $|V_{ov}| = 0.3$ V, so inverting the saturation equation, $$\left(\frac{W}{L}\right)_{2}=\frac{2I_{bias}}{\mu_p C_{ox}|V_{ov}|^2} =\frac{2(200\times10^{-6})}{(100\times10^{-6})(0.3)^2} =\frac{400\times10^{-6}}{9\times10^{-6}}$$ giving $\boxed{(W/L)_{2}=44.4}$, i.e. a drawn width $W_2 = 44.4 \times 0.36 = 16$ µm at the specified $L_p = 0.36$ µm.
Find the voltage at the shared node, because that is what sizes $M_1$. $M_2$ is diode-connected, so its gate–source magnitude is fixed by its overdrive, $|V_{GS2}| = |V_{TH}| + |V_{ov}| = 0.5 + 0.3 = 0.8$ V, and the node it shares with $M_1$ therefore sits at $$V_X = V_{DD} - |V_{GS2}| = 3.0 - 0.8 = 2.2\ \text{V}$$ Both devices are diode-connected, so each has $V_{DS}$ equal to its own $V_{GS}$ and both are saturated by construction — no separate saturation check is needed.
The NMOS overdrive is not free — the stack has already spent it. $M_1$ is also diode-connected, so its gate–source voltage is $V_X$, and its overdrive follows: $$V_{ov1} = V_X - V_{TH} = 2.2 - 0.5 = 1.7\ \text{V}$$ This is the step the question is really testing. The paper specifies an overdrive only for the p-channel devices; the NMOS overdrive is whatever the supply has left after $M_2$ has taken its share, and it comes out very large.
Size $M_1$ at that overdrive. Inverting the square law once more, this time with the electron parameter, $$\left(\frac{W}{L}\right)_{1}=\frac{2I_{bias}}{\mu_n C_{ox}V_{ov1}^2} =\frac{2(200\times10^{-6})}{(400\times10^{-6})(1.7)^2} =\frac{400\times10^{-6}}{1156\times10^{-6}}$$ which gives $\boxed{(W/L)_{1}=0.346}$ — less than unity, so the device must be longer than it is wide.
Choose a realisable geometry, which is what the note in the question is for. With $(W/L)_1 = 0.346$, holding $L$ at the 0.36 µm used elsewhere would demand $W_1 = 0.125$ µm, below the 0.18 µm minimum feature of the process. The paper anticipates this by permitting a longer channel, so take a comfortable width and let the length follow: $$L_1 = \frac{W_1}{(W/L)_1} = \frac{0.5\ \mu\text{m}}{0.346} = 1.45\ \mu\text{m}$$ taking $W_1 = 0.5$ µm, that is $\boxed{W_1/L_1 = 0.5\ \mu\text{m}\,/\,1.45\ \mu\text{m}}$. Any pair in the same ratio serves; the long channel is a bonus here because it also raises the Early voltage of the reference device.
Part (b) — scale the output devices by their current ratios. $M_3$ and $M_4$ share both their source (at $V_{DD}$) and their gate (at $V_X$) with $M_2$, so all three have the identical $|V_{GS}|$ and hence the identical overdrive. In the square law the only remaining freedom is the aspect ratio, so current ratios are width ratios. From $I_3 = 8I_{bias} = 1.6$ mA and $I_4 = I_3/4 = 400$ µA, $$\begin{aligned} \left(\frac{W}{L}\right)_{3} &= 8\left(\frac{W}{L}\right)_{2} = 8(44.4) = 355.6 \\[2pt] \left(\frac{W}{L}\right)_{4} &= 2\left(\frac{W}{L}\right)_{2} = 2(44.4) = 88.9 \end{aligned}$$ so $\boxed{(W/L)_{3}=355.6,\ (W/L)_{4}=88.9}$, i.e. $W_3 = 128$ µm and $W_4 = 32$ µm at $L_p = 0.36$ µm. Their ratio is 4:1, reproducing $I_3 = 4I_4$ as required.
Part (c) — identify the only mechanism that lets $I_3$ move. $M_3$ is a saturated current source with a fixed gate drive, so its current would be perfectly constant were it not for channel-length modulation. The paper’s own formula sheet gives the incremental resistance of that effect as $$r_{o3} = \frac{1}{\lambda I_3} = \frac{1}{(0.2)(1.6\times10^{-3})} = 3.125\ \text{k}\Omega$$ and the swing at the drain is $\Delta V_3 = 1.5 - 0 = 1.5$ V.
Convert the voltage swing into a current change. Driving that resistance with the full swing, $$\Delta I_3 = \frac{\Delta V_3}{r_{o3}} = \frac{1.5}{3125} = 4.80\times10^{-4}\ \text{A}$$ so $\boxed{\Delta I_3 \approx 480\ \mu\text{A}}$, which is 30 percent of the nominal 1.6 mA. Note the sign: raising $V_3$ reduces the source–drain voltage of the PMOS and so reduces $I_3$, and the current is largest when $V_3 = 0$.
Sharpen the figure by working from the saturation law directly. Because $I_D = I_{D0}\,(1+\lambda|V_{SD}|)$ is linear in $|V_{SD}|$, the endpoints can be computed exactly once the reference point is pinned. The 8:1 ratio holds exactly where $M_3$ sees the same $|V_{SD}|$ as the diode-connected $M_2$, namely 0.8 V, so $I_{D0} = 1.6\ \text{mA}/(1+0.2 \times 0.8) = 1.379$ mA and $$\begin{aligned} I_3(V_3 = 0) &= 1.379\,[1+0.2(3.0-0)] = 2.207\ \text{mA} \\[2pt] I_3(V_3 = 1.5) &= 1.379\,[1+0.2(3.0-1.5)] = 1.793\ \text{mA} \end{aligned}$$ giving an exact change of 414 µA, or 25.9 percent of the 1.6 mA design value. The two answers differ only by the factor $(1+\lambda|V_{GS2}|) = 1.16$, which is the price of evaluating $r_o$ at the nominal current rather than at the zero-bias current; the 480 µA figure is the conservative one and is what the paper’s own formula delivers.
Check that $M_3$ never leaves saturation over the swing. The source is at $V_{DD} = 3.0$ V, so saturation requires $|V_{SD3}| = 3.0 - V_3 \ge |V_{ov}| = 0.3$ V, i.e. $V_3 \le 2.7$ V. The specified swing stops at 1.5 V, comfortably inside that compliance limit, so the linear channel-length-modulation model used above is valid across the whole range. Had $V_3$ been allowed above 2.7 V the current would have collapsed far faster than any $r_o$ calculation predicts.

Check: device types in the reference branch. The reading used above — PMOS $M_2$ (source at $V_{DD}$) in series with NMOS $M_1$ (source at ground), both diode-connected onto one node that drives the PMOS sources $M_3$ and $M_4$ — is the only one that is self-consistent with the printed data, because it is the only one in which (i) $M_3$ and $M_4$ can have a defined current at all, since a PMOS current source needs a diode-connected PMOS reference, (ii) the given “$L = 0.36$ µm for the p-channel transistors” leaves $M_1$’s length free, and (iii) the note that “the channel length for transistor M1 can be 0.36 µm or longer” earns its place, which it does only because $(W/L)_1 < 1$ forces exactly that.

Quantity	Result
(a) $(W/L)_2$ — diode-connected PMOS	44.4 ($W_2 = 16$ µm at $L = 0.36$ µm)
(a) Reference-node voltage $V_X$	2.2 V ($\|V_{GS2}\| = 0.8$ V)
(a) NMOS overdrive forced by the stack	$V_{ov1} = 1.7$ V
(a) $(W/L)_1$ — diode-connected NMOS	0.346 (e.g. $W_1 = 0.5$ µm, $L_1 = 1.45$ µm)
(b) $(W/L)_3$ for $I_3 = 1.6$ mA	355.6 ($W_3 = 128$ µm)
(b) $(W/L)_4$ for $I_4 = 400$ µA	88.9 ($W_4 = 32$ µm)
(c) Output resistance $r_{o3} = 1/(\lambda I_3)$	3.125 k$\Omega$
(c) Variation of $I_3$ over $V_3 = 0$ to 1.5 V	$\Delta I_3 \approx 480$ µA (30 percent of 1.6 mA)
(c) Exact endpoints from the saturation law	2.207 mA at $V_3 = 0$; 1.793 mA at $V_3 = 1.5$ V ($\Delta = 414$ µA)
(c) Compliance limit on $V_3$	$V_3 \le V_{DD} - \|V_{ov}\| = 2.7$ V

Topic. CMOS current-source biasing: setting a reference from a diode stack, ratioing outputs by device width, and the compliance and output resistance that channel-length modulation imposes.

Key relations. $I_D = \tfrac12\mu C_{ox}(W/L)V_{ov}^2(1+\lambda|V_{DS}|)$; $|V_{GS}| = |V_{TH}| + |V_{ov}|$; for devices sharing a gate and a source, $I_A/I_B = (W/L)_A/(W/L)_B$; $r_o = 1/(\lambda I_D)$; $\Delta I \approx \Delta V/r_o$; saturation requires $|V_{DS}| \ge |V_{ov}|$, so the compliance range is $V_{DD} - |V_{ov}|$.

Why this works. A current mirror is an exercise in cancellation. Two devices that share a gate and a source have identical gate–source voltages, so in the square law every process- and temperature-dependent term — $\mu C_{ox}$, $V_{TH}$, the overdrive itself — is common to both and divides out, leaving only the geometric ratio, which is set by lithography and is stable to a fraction of a per cent. That is why a mirror can deliver an 8:1 ratio accurately when no absolute quantity in the circuit is known to better than 20 per cent. The residual error is channel-length modulation, which does not cancel, because the two devices generally sit at different drain voltages; it is the reason a plain mirror has a finite output resistance and the reason cascoding exists. The stacked-diode reference used here is the cheapest way to generate the gate voltage, but note what it costs: the NMOS gets whatever overdrive the supply has left, here a very large 1.7 V, which is why its aspect ratio came out below unity.

Common pitfall. Assuming the NMOS shares the specified 0.3 V overdrive — the paper says “for all the p-channel transistors”, and the NMOS overdrive is a consequence, not a specification. Reading the note about $M_1$’s channel length as a hint that something is wrong, when it is in fact confirmation that $(W/L)_1 < 1$ is expected. And in part (c), quoting the current change without checking the compliance limit: the linear $r_o$ model is only valid while $M_3$ stays saturated, and a candidate who reports a number for a swing that would drive the device into triode has answered a different question.

Source. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., Sections 5.1–5.2 (basic current mirrors, ratioing and the effect of channel-length modulation); P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Section 4.2 (MOS current mirrors and output resistance); R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 4th ed., Ch. 20 (current mirrors and their compliance).

Question 4 of 5: CMOS Current-Source Bias Generator — Sizing, Ratioing and Compliance

Question 4: CMOS Current-Source Bias Generator — Sizing, Ratioing and Compliance (20 marks)