Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Phys-A5-B — Analog and Digital Electronic Circuits — National Exams, May 2019
3 hours duration. Open book exam. Answer all SIX (6) questions.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (diode limiting circuits Ch. 4, BJT biasing and common-base amplifiers Ch. 6, MOSFET differential amplifiers and current mirrors Ch. 7–8, frequency response Ch. 9, feedback amplifiers Ch. 10, D/A converters Ch. 17); M. M. Mano & M. D. Ciletti, Digital Design, 6th ed. (Boolean algebra Ch. 2, static CMOS logic gates Ch. 10).
Given. Differential pair $M_1$ (gates $v_{G1}=v_{cm}+v_{id}/2$, $v_{G2}=v_{cm}-v_{id}/2$), each drain loaded by $R_D$ in parallel with a PMOS $M_2$ whose gate is tied to a fixed DC bias $V_b$ (source at $V_{DD}$) — NOT diode-connected. The $M_1$ pair's common source (tail) is set by $M_3$, mirrored from $I_{bias}$ through diode-connected $M_4$. $v_o$ is the differential output between the two drains. All four transconductances and all four output resistances are stated as mutually unequal ($g_{m1}\ne g_{m2}\ne g_{m3}\ne g_{m4}$, likewise for $r_o$) — only $g_{m1}$, $r_{o1}$, $r_{o2}$ end up in the differential-mode result. Parasitics given: $C_{gs}$ only (no $C_{gd}$) on every transistor.
Find. (a) $A_d=|v_o/v_{id}|$. (b) $f_H$ including all four $C_{gs}$.
Fig. 3 — MOS diff pair with fixed-$V_b$ PMOS loads $M_2$ and an $M_3/M_4$ current-mirror tail referenced to $I_{bias}$.
Approach. Use the differential half-circuit: identify the effective drain load (noting $M_2$ degenerates to a plain resistor because both its gate and source are AC grounds), get $A_d$; then check, node by node, whether each given $C_{gs}$ actually bridges two different-voltage nodes before claiming it sets a pole.
Part (a) — load seen by $M_1$'s drain. $M_2$'s gate sits at the fixed bias $V_b$ (AC ground) and its source sits at $V_{DD}$ (AC ground), so $v_{gs2}=0$ for any signal: $M_2$ carries only $i_{d2}=v_{ds2}/r_{o2}$, i.e. it behaves as a plain resistor $r_{o2}$ from the drain node to ground. The total small-signal load at each output is therefore $R_D\parallel r_{o1}\parallel r_{o2}$ (the tail node is a virtual AC ground for differential excitation, so $M_1$'s own $r_{o1}$ appears from drain to that ground).
Half-circuit gain. Each half-circuit is a common-source stage with $g_{m1}$ driving that load: $$\boxed{A_d=\left|\frac{v_o}{v_{id}}\right| = g_{m1}\left(R_D\parallel r_{o1}\parallel r_{o2}\right)}$$ ($v_o$ is the full differential output, so the two half-circuit swings add: $v_o=v_{o1}-v_{o2}=-g_{m1}v_{id}(R_D\parallel r_{o1}\parallel r_{o2})$.)
Part (b) — where does each $C_{gs}$ actually connect? $C_{gs1}$ bridges the input gate (driven by an ideal voltage source, zero output impedance) and the tail (a virtual AC ground under differential excitation) — both ends are AC-equivalent to a fixed potential, so it carries displacement current between two zero-impedance nodes without perturbing the voltage anywhere else in the circuit. $C_{gs2}$ bridges $V_b$ (AC ground) and $V_{DD}$ (AC ground) — both ends grounded. $C_{gs3}$ and $C_{gs4}$ sit entirely inside the tail/mirror sub-circuit, which by symmetry carries no differential-mode current at all.
Conclusion. None of the four given $C_{gs}$ bridges the output node to a node at a different differential-mode potential, so none contributes a pole to $A_d(s)$: $$\boxed{f_H\to\infty\ \text{under this parasitic model}}$$ The real bandwidth limit in this topology comes from $C_{gd}$ (Miller-multiplied across the gain stage), which the question deliberately excludes.
