17-Phys-A5, Undated paper, Q6

Question 6 (15 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Four logic inputs $A,B,C,D$; target function $Y=A\cdot B\cdot C+D$ (AND of three, ORed with a fourth).

Find. A static CMOS transistor-level schematic (PDN + PUN, clearly labelled) implementing $Y$.

Fig. 6 — AND-OR-INVERT (AOI) gate: PDN = $(A,B,C$ in series$)\parallel D$ pulls the internal node $Y'$ low exactly when $ABC+D=1$; PUN is its series/parallel dual. A final inverter restores the true (non-inverted) $Y$.

Approach. Any static CMOS gate is naturally inverting, so first build the AND–OR–INVERT (AOI) network that realizes $Y'=\overline{A\cdot B\cdot C+D}$ directly from the Boolean expression (series=AND, parallel=OR in the NMOS pull-down; the PMOS pull-up is the exact series/parallel dual), then append one inverter stage to recover the non-inverted $Y$ the question asks for.

Pull-down network (PDN, NMOS). The PDN must conduct (pull the internal node $Y'$ to 0) exactly when $A\cdot B\cdot C+D=1$. Series NMOS realize AND, parallel branches realize OR: put NMOS $A$, $B$, $C$ in series (conducts only when $A=B=C=1$), and put NMOS $D$ in parallel with that series chain (conducts whenever $D=1$). $$Y' = \overline{A\cdot B\cdot C + D}$$
Pull-up network (PUN, PMOS) — the dual. Standard CMOS duality: series in the PDN becomes parallel in the PUN, and parallel becomes series. So PMOS $A$, $B$, $C$ are wired in PARALLEL with each other, and that group is in SERIES with PMOS $D$, between $V_{DD}$ and $Y'$. This conducts (pulls $Y'$ high) exactly when $D=0$ AND at least one of $A,B,C=0$ — the exact logical complement of the PDN's conduction condition, so $Y'$ is always driven to a valid logic level for all 16 input combinations.
Restore the non-inverted output. A static CMOS network always produces the complement of what its PDN pulls down on; since the question asks for $Y$ itself (not $Y'$), append one standard CMOS inverter (one NMOS + one PMOS, gates tied to $Y'$) so that $$\boxed{Y = \overline{Y'} = \overline{\overline{A\cdot B\cdot C+D}} = A\cdot B\cdot C+D}$$

Network	Topology
PDN (NMOS)	$(A\text{-}B\text{-}C$ series$)\parallel D$, between $Y'$ and GND
PUN (PMOS)	$(A\parallel B\parallel C)$ in series with $D$, between $V_{DD}$ and $Y'$
Internal node	$Y'=\overline{A\cdot B\cdot C+D}$
Final output (after inverter)	$Y=A\cdot B\cdot C+D$

Concept & Theory

Topic: static CMOS complex-gate synthesis (AND-OR-INVERT).

Key relations: PDN series=AND / parallel=OR (NMOS, active-high conduction); PUN is the exact series–parallel dual (PMOS, active-low conduction); every static CMOS network is inherently inverting.

Why this works: duality guarantees that for every input combination exactly one of the PDN/PUN paths conducts and the other is open, so the output node is always driven to a solid 0 or 1 (no floating/contention states) — this is the defining property that makes static CMOS gates ratioless and robust.

Common pitfall: forgetting that a single AOI gate produces the COMPLEMENT of the target function and submitting $Y'$ as if it were $Y$; or building the PUN as a literal mirror of the PDN's series/parallel structure instead of its dual.

Source: Mano & Ciletti, Digital Design, Ch. 10 (static CMOS logic gates, complex AOI gates).

Question 6 of 6

Question 6 (15 marks)