98-Phys-A5, May 2015, Q4 | Nivaar Exam Prep

Question 4 (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A MOSFET common-source stage (Figure P4) biased at $I_D=1\,\text{mA}$, $V_{DS}=10\,\text{V}$, with the component values below.

Symbol	Value
$V_{DD}$	20 V
$R_D$, $R_L$	5 kΩ each
$R_S$	5 kΩ
$R_{sig}$	1 kΩ
$C_i$	0.01 µF
$C_S$	100 µF
$I_D$, $V_{GS}$, $g_m$, $r_o$	1 mA, 1 V, 4 mA/V, 500 kΩ

Find. (a) role of the coupling/bypass capacitors; (b) $R_{out}$; (c) $R_1$, $R_2$; (d) $A_{vm}=v_o/v_{sig}$; (e) $C_o$ for $\omega_{p3}$ dominant.

Figure — mid-band small-signal equivalent circuit (all coupling/bypass capacitors replaced by short circuits): $R_{out}$ is the resistance looking left into the drain node before $C_o$.

Approach. (b) at mid-band every capacitor is a short, so $R_{out}$ is just what the $R_L$ branch sees looking back into the drain: $R_D\Vert r_o$. (c) the DC gate voltage from the $R_1$/$R_2$ divider must equal $V_{GS}+I_DR_S$, while $R_1\Vert R_2=R_{in}$; two equations, two unknowns. (d) with all capacitors shorted, $A_{vm}$ is the input-divider attenuation times $-g_m$ times the total drain-side parallel resistance. (e) size $C_o$ so $\omega_{p3}$ sits at least a decade above the other low-frequency singularities, making it the dominant (highest-frequency) pole.

Part (a) — role of the capacitors. $C_i$ and $C_o$ are DC-blocking coupling capacitors: they pass the AC signal while isolating the amplifier's own DC bias point from the signal source and the load, so $R_1$, $R_2$ and $R_S$ can set $I_D$ and $V_{GS}$ independently of whatever is connected at the input/output. $C_S$ is a bypass capacitor: it AC-shorts $R_S$ at signal frequencies (while $R_S$ still sets the DC bias), removing the source-degeneration gain loss that $R_S$ would otherwise cause.
Part (b) — $R_{out}$. Looking back into the drain node from $R_L$ (Figure above), with $v_{sig}=0$, the dependent source $g_mv_{gs}$ contributes zero current (its controlling $v_{gs}=0$), leaving only $R_D$ and $r_o$ in parallel: $$R_{out}=R_D\Vert r_o=\frac{(5\,\text{k})(500\,\text{k})}{5\,\text{k}+500\,\text{k}}=\boxed{4.95\ \text{k}\Omega}$$
Part (c) — $R_1$, $R_2$. The DC source voltage is $V_S=I_DR_S=(1\,\text{mA})(5\,\text{k}\Omega)=5\,\text{V}$, so the required gate voltage is $V_G=V_{GS}+V_S=1+5=6\,\text{V}$. With $V_G=V_{DD}\dfrac{R_2}{R_1+R_2}$ and $R_1\Vert R_2=420\,\text{k}\Omega$: $$\frac{R_2}{R_1+R_2}=\frac{6}{20}=0.30\qquad R_1\Vert R_2=0.30(1-0.30)(R_1+R_2)=420\,\text{k}\Omega\ \Rightarrow\ R_1+R_2=2\,\text{M}\Omega$$ $$R_1=0.70(2\,\text{M}\Omega)=\boxed{1.4\ \text{M}\Omega}\qquad R_2=0.30(2\,\text{M}\Omega)=\boxed{600\ \text{k}\Omega}$$ (Check: $R_1\Vert R_2=420\,\text{k}\Omega$; $V_G=20(600\text{k}/2\text{M})=6\,\text{V}$. ✓)
Part (d) — midband gain $A_{vm}=v_o/v_{sig}$. At mid-band all capacitors are shorts, so $v_{gs}$ equals the gate voltage (the bypassed source sits at AC ground), and the drain sees $R_D\Vert R_L\Vert r_o$: $$R_D\Vert R_L\Vert r_o=\frac{1}{\frac{1}{5\text{k}}+\frac{1}{5\text{k}}+\frac{1}{500\text{k}}}=2487.6\ \Omega$$ The signal first divides down at the gate through $R_{sig}=1\,\text{k}\Omega$ and $R_{in}=420\,\text{k}\Omega$ (gate draws no current): $$A_{vm}=\frac{R_{in}}{R_{in}+R_{sig}}\times\big(-g_m(R_D\Vert R_L\Vert r_o)\big)=\frac{420}{421}\times\big(-4\times10^{-3}\times2487.6\big)$$ $$A_{vm}=(0.99762)(-9.950)=\boxed{-9.93\ \text{V/V}}$$
Part (e) — $C_o$ for a dominant $\omega_{p3}$. With $R_1$, $R_2$ from part (c), the other two low-frequency break frequencies are $$\omega_{p1}=\frac{1}{(R_{sig}+R_{in})C_i}=\frac{1}{(421\,\text{k})(0.01\,\mu\text{F})}=237.5\ \text{rad/s}$$ $$\omega_{p2}=\frac{1}{\left(R_S\Vert\frac{1}{g_m}\right)C_S}=\frac{1}{(238.1\,\Omega)(100\,\mu\text{F})}=42.0\ \text{rad/s}$$ For $\omega_{p3}$ to dominate (sit well above both), require $\omega_{p3}\gtrsim10\,\omega_{p1}\approx2400\,\text{rad/s}$: $$C_o\le\frac{1}{\omega_{p3}(R_{out}+R_L)}=\frac{1}{(2400)(9.95\,\text{k}\Omega)}\approx4.2\times10^{-8}\,\text{F}$$ Choosing the standard value $C_o=\boxed{0.033\ \mu\text{F}}$ gives $\omega_{p3}=1/[(9.95\,\text{k})(0.033\,\mu\text{F})]\approx3045\,\text{rad/s}$, about 13× $\omega_{p1}$ and 72× $\omega_{p2}$ — clearly the dominant (highest-frequency) low-frequency singularity, so it alone sets the amplifier's lower cutoff.

Quantity	Value
$R_{out}$	4.95 kΩ
$R_1$, $R_2$	1.4 MΩ, 600 kΩ
$A_{vm}=v_o/v_{sig}$	−9.93 V/V
$C_o$ (for dominant $\omega_{p3}$)	0.033 µF ($\omega_{p3}\approx3045\,\text{rad/s}$)

Concept & Theory

Topic: MOSFET common-source amplifier: gate-divider biasing, mid-band small-signal gain, and open-circuit time-constant pole placement.

Key relations: $V_G=V_{DD}\dfrac{R_2}{R_1+R_2}$; $R_{in}=R_1\Vert R_2$; $A_{vm}=-g_m(R_D\Vert R_L\Vert r_o)\cdot\dfrac{R_{in}}{R_{in}+R_{sig}}$; each coupling/bypass RC pair contributes an independent pole $\omega=1/(R_{eq}C)$.

Why this works: the MOSFET gate draws no DC current, so the bias point depends only on the resistive divider and $R_S$; at mid-band every capacitor is a short, collapsing the circuit to a pure resistive small-signal model; at low frequency, each RC pair independently sets one corner frequency (open-circuit time-constant method), and making one pole a decade above the others lets it alone determine the amplifier's $-3\,\text{dB}$ point.

Common pitfall: computing $A_{vm}$ as $v_o/v_i$ (gate voltage) instead of $v_o/v_{sig}$, which omits the $R_{in}/(R_{in}+R_{sig})$ input-divider factor; and forgetting to add $V_S=I_DR_S$ to $V_{GS}$ when finding the required gate voltage $V_G$.

Source: Sedra & Smith, Microelectronic Circuits, Ch. 7 (MOSFET amplifiers, biasing and frequency response).

Question 4 of 7

Question 4 (20 marks)