98-Phys-A5, May 2015, Q5 | Nivaar Exam Prep

Question 5 (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Figure P5a: a single BJT with a collector pull-up resistor to $V_{CC}$ and a base resistor from $V_i$. Figure P5b: two NMOS transistors — the top one has its gate tied to $V_{DD}$ (its own drain rail), acting as an enhancement (saturated) load; the bottom one is the switching driver, gated by $V_i$. Figure P5c: a PMOS on top and an NMOS on the bottom, gates tied together and driven by $V_i$ (CMOS). Figure P5d: VTC with $V_{OH}=3.0\,\text{V}$, $V_{OL}=0\,\text{V}$ on a $0$–$3.0\,\text{V}$ input/output scale. Figure P5e: five identical inverters in a ring, output fed back to the first input; $T=20\,\text{ns}$ is the period of the resulting periodic signal $v(t)$.

Find. (a) logic family names; (b) one advantage + one disadvantage per family; (c) $NM_L$, $NM_H$, switching voltage, gain (from the VTC); (d) name of the P5e circuit, the rise/fall-time asymmetry reason, and $t_{pd}$.

[Figure not reproduced: Figure — the three inverter topologies of Figures P5a/b/c, redrawn. See the official exam paper.]

[Figure not reproduced: Figure P5d, redrawn — VTC with the graphically-estimated $V_{IL}$, $V_{IH}$ (unity-slope points) and switching voltage $V_M$ marked; the dashed diagonal is $V_o=V_i$. See the official exam paper.]

Approach. (a)/(b) identify each family from its transistor/resistor topology and recall its standard trade-off. (c) read $V_{IL}$, $V_{IH}$ (the points where the VTC's slope is $-1$) and the switching voltage $V_M$ (where $V_o=V_i$) directly off the curve, then $NM_L=V_{IL}-V_{OL}$, $NM_H=V_{OH}-V_{IH}$, and the gain is the slope's magnitude through the transition. (d) a ring of an odd number of inverters with output fed back to input is a ring oscillator; its period relates to the per-stage delay by $T=2N\,t_{pd}$.

Part (a) — logic families. Figure P5a (single BJT with resistor collector load and a base resistor) is RTL — Resistor-Transistor Logic (bipolar saturating logic). Figure P5b (two NMOS transistors, the top one's gate tied to $V_{DD}$ as an enhancement/saturated load) is NMOS logic with an enhancement (saturated) load. Figure P5c (complementary PMOS-on-top / NMOS-on-bottom pair, gates tied together) is CMOS.
Part (b) — one advantage / one disadvantage each. RTL: advantage — simple, mature bipolar process with strong output drive; disadvantage — the pull-up resistor always conducts some current (static power dissipation) and BJT saturation causes a slow storage-time turn-off, limiting speed. NMOS, enhancement load: advantage — needs only one transistor type (simpler, denser fabrication than CMOS); disadvantage — the load transistor conducts whenever the driver is ON (static power dissipation), and $V_{OH}$ does not reach the full $V_{DD}$ (a threshold-voltage drop across the load), reducing the high noise margin. CMOS: advantage — essentially zero static (DC) power dissipation and full rail-to-rail output swing (best noise margins); disadvantage — needs both transistor types (larger area, more complex, more masks) and is susceptible to latch-up.
Part (c) — graphical VTC extraction. Reading the transition region of Figure P5d, the unity-slope ($dV_o/dV_i=-1$) points fall at approximately $V_{IL}\approx0.9\,\text{V}$ and $V_{IH}\approx1.4\,\text{V}$, giving $$NM_L=V_{IL}-V_{OL}=0.9-0=\boxed{0.9\ \text{V}}\qquad NM_H=V_{OH}-V_{IH}=3.0-1.4=\boxed{1.6\ \text{V}}$$ The curve crosses the $V_o=V_i$ diagonal at $V_M\approx\boxed{1.2\ \text{V}}$ (switching voltage). The gain is the slope of the VTC in its transition region, taken where the curve is steepest, around $V_M$: $V_o$ falls from about $2.1\,\text{V}$ at $V_i\approx1.11\,\text{V}$ to about $0.8\,\text{V}$ at $V_i\approx1.20\,\text{V}$, so $$A_v=\left.\frac{dV_o}{dV_i}\right|_{V_M}\approx\frac{0.8-2.1}{1.20-1.11}\approx\boxed{-14\ \text{V/V}}$$ The cruder piecewise-linear average $(V_{OH}-V_{OL})/(V_{IH}-V_{IL})=3.0/0.5=6$ spreads the whole 3 V swing over the $V_{IL}$–$V_{IH}$ window, so it understates the small-signal gain at the switching point by a factor of about 2.3; quote the tangent slope at $V_M$.
Part (d)(i) — name of the P5e circuit. Five identical inverters connected in a chain with the last stage's output fed back to the first stage's input, and no external clock, is a 5-stage ring oscillator.
Part (d)(ii) — why rise time differs from fall time. The pull-up path (resistor/load transistor charging the next stage's input capacitance HIGH) and the pull-down path (driver transistor discharging it LOW) generally have different effective drive resistances/currents — e.g. a PMOS pull-up is normally weaker than an NMOS pull-down of the same size (lower hole mobility), or in RTL/NMOS-load logic the passive/load pull-up is inherently weaker than the active driver pull-down. Since each transition is an RC charge or discharge of the next stage's load capacitance through a different effective resistance, the rise time and fall time are unequal.
Part (d)(iii) — average propagation delay. Going once around an $N$-stage inverter ring inverts the signal; going around twice ($2N$ inverter delays) restores the original polarity and completes one full period: $$T=2N\,t_{pd}\ \ \Rightarrow\ \ t_{pd}=\frac{T}{2N}=\frac{20\,\text{ns}}{2(5)}=\boxed{2\ \text{ns}}$$

Check

$V_{IL}$, $V_{IH}$, $V_M$ and the gain in part (c) are graphically estimated from the exam's own printed VTC (Figure P5d) to the precision a hand-drawn tangent construction allows; the qualitative method (locate the $-1$-slope points, read $V_o=V_i$) is exact even though the last digit of each read-off value is an estimate.

Quantity	Value
(a) Families P5a / P5b / P5c	RTL / NMOS enh. load / CMOS
(c) $NM_L$, $NM_H$	0.9 V, 1.6 V
(c) Switching voltage $V_M$	≈ 1.2 V
(c) Gain	≈ −14 V/V (slope at $V_M$)
(d) Circuit name	5-stage ring oscillator
(d) $t_{pd}$	2 ns

Concept & Theory

Topic: Logic-family inverter topologies, VTC noise-margin figures of merit, and ring-oscillator timing.

Key relations: $NM_L=V_{IL}-V_{OL}$; $NM_H=V_{OH}-V_{IH}$ ($V_{IL}$, $V_{IH}$ = unity-slope points on the VTC); gain $\approx dV_o/dV_i$ through the transition; ring-oscillator $T=2N\,t_{pd}$ ($N$ = odd stage count).

Why this works: noise margins quantify how much a logic level can be corrupted before the next gate might misread it — defined exactly at the points where the VTC's slope crosses $-1$, because any region with $|slope|>1$ would amplify noise rather than attenuate it. An odd-stage inverter ring has no stable DC state: one full trip inverts the signal, so it takes two full trips ($2N$ stage delays) to return to the starting logic level, which is the oscillation period.

Common pitfall: swapping which bound goes with which noise margin ($NM_L$ uses $V_{IL}$, not $V_{IH}$); and forgetting the factor of 2 in the ring-oscillator period formula (using $T=N\,t_{pd}$ instead of $2N\,t_{pd}$).

Source: Mano & Ciletti, Digital Design, Ch. 10 (CMOS/NMOS logic-family gates).

Question 5 of 7

Question 5 (20 marks)