Question 6 of 7

Question 6 (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

[Figure not reproduced: Figure P6, redrawn as a block diagram — the comparator-bank + priority-encoder + latch structure is a flash (parallel) ADC. See the official exam paper.]

Approach. Recognize the architecture from the parallel comparator bank feeding a priority encoder (no successive iteration, no clocked bit-cycling). Convert the required $0.25^\circ\text{C}$ resolution into volts using the transducer's linear scale, then find the smallest $n$ whose LSB is fine enough.

1. Part (a) — ADC type and disadvantage. A bank of $2^n-1$ comparators, each tapping a different reference level off a resistor ladder and feeding a priority encoder, is a flash (parallel) ADC. Its main disadvantage is that it needs $2^n-1$ comparators (and $2^n-1$ resistor taps): the component count, chip area and static power grow exponentially with the number of bits $n$, making high resolution impractical.
2. Part (b) — what limits conversion speed. Because every reference level is compared to $V_A$ simultaneously, a flash ADC needs no bit-by-bit clock cycles (unlike successive-approximation or dual-slope converters) — it is inherently the fastest ADC architecture for a given $n$. Its actual conversion speed is limited only by the analog settling/response time of the comparators themselves and the digital propagation delay through the priority encoder and output latch.
3. Part (c) — minimum number of bits. A resolution of $0.25^\circ\text{C}$, converted through the transducer's linear $3\,\text{V}/30^\circ\text{C}$ scale, is $$\Delta V=0.25^\circ\text{C}\times\frac{3\,\text{V}}{30^\circ\text{C}}=25\,\text{mV}$$ The ladder in Figure P6 has $R/2$ at both ends and $R$ between the $2^n-1$ taps, so its total resistance is $(2^n-1)R$ and the taps sit at $V_{rk}=(k-\tfrac12)V_{ref}/(2^n-1)$: the step size is $\text{LSB}=V_{ref}/(2^n-1)$, with each threshold half an LSB above a code centre (a rounding quantizer). We need $V_{ref}/(2^n-1)\le\Delta V$: $$2^n-1\ge\frac{V_{ref}}{\Delta V}=\frac{3.1}{0.025}=124\ \ \Rightarrow\ \ 2^n\ge125\ \ \Rightarrow\ \ \boxed{n=7\ \text{bits}}$$ ($2^6-1=63<124$ is not enough; $2^7-1=127\ge124$ works. The simpler $V_{ref}/2^n$ estimate gives the same $n$.)
4. Part (d) — the digital signal. With $n=7$, the digital word ranges over $2^7=128$ codes, from $0000000_2$ (0 °C) up to $1111111_2$ (127 decimal). The actual LSB achieved is $$\text{LSB}=\frac{V_{ref}}{2^n-1}=\frac{3.1}{127}=24.41\,\text{mV}\ \leftrightarrow\ 0.244^\circ\text{C per bit}$$ — finer than the required $0.25^\circ\text{C}$, confirming $n=7$ meets the spec. At the top of the specified range, $T=30^\circ\text{C}$ ($V_A=3\,\text{V}$), the code sent to the thermostat is the number of comparators whose threshold lies below $V_A$: $(k-\tfrac12)(24.41\,\text{mV})<3\,\text{V}$ gives $k<123.4$, so comparators 1 to 123 fire and $$\text{code}=\mathrm{round}\!\left(\frac{V_A}{\text{LSB}}\right)=\mathrm{round}\!\left(\frac{3}{0.02441}\right)=\mathrm{round}(122.9)=123\ (\text{decimal})=\boxed{1111011_2}$$ (Taking the LSB as $V_{ref}/2^n=24.2\,\text{mV}$ instead would give $\mathrm{round}(123.9)=124$; that step size does not match the $R/2$-ended ladder actually drawn.)