Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Phys-A5 — Semiconductor Devices & Circuits — National Exams, May 2017
3 hours duration. Closed book exam (useful constants, equations and device models are annexed to the exam paper). Any FIVE (5) of the SEVEN (7) questions constitute a complete exam paper; all seven are answered here as a complete study resource.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (semiconductor/diode physics Ch. 3–4, op-amp and active-filter circuits Ch. 2 & 12, MOSFET small-signal amplifiers Ch. 7, data converters Ch. 17, precision rectifiers Ch. 4); M. M. Mano & M. D. Ciletti, Digital Design, 6th ed. (CMOS logic-family gates Ch. 10); C. Kittel, Introduction to Solid State Physics, 8th ed. (semiconductor carrier transport and statistics Ch. 8).
Given. CMOS inverter, $V_{DD}=3\,\text{V}$, $(W/L)_p=(W/L)_n=2$; the exam's own VTC plot shows a sharp transition centred near $V_i\approx1.1\,\text{V}$; a 5-stage ring oscillator built from identical copies of this inverter.
Symbol
Value
$V_{DD}$
3 V
$k_n/k_p$ (part b)
3
$V_{tn}$
0.4 V
$V_{tp}$
−0.5 V
$t_{phl}$, $t_{plh}$
1.8 ns, 2.2 ns
Ring stages $N$
5
Find. (a) $NM_L$, $NM_H$, $V_x$, gain (graphical); (b) exact $V_x$; (c) modification for $V_x=1.5\,\text{V}$; (d) ring-oscillator frequency.
[Figure not reproduced: Figure P5a (exam figure). See the official exam paper or the cited reference text.]
Figure P5a (exam figure) — CMOS inverter and its VTC; the grid pitch is 0.3 V on both axes.
[Figure not reproduced: Figure P5b (exam figure). See the official exam paper or the cited reference text.]
Figure P5b (exam figure) — 5-stage ring oscillator; node N is the input of the fifth inverter and $v(t)$ is taken from N.
Approach. (a) read the VTC directly at the marked features. (b) set $I_{Dn}=I_{Dp}$ with both devices saturated at the switching point and solve for $V_x$. (c) use the same equal-currents condition to see which device needs to be strengthened/weakened. (d) an odd number of inverting stages self-oscillates; the period is twice the sum of each stage's average propagation delay times the number of stages.
Part (a) — graphical VTC read-off. Digitizing the plotted curve of Figure P5a (0.3 V grid on both axes): $V_{OH}=3.0\,\text{V}$ for $V_i\lesssim0.5\,\text{V}$, $V_{OL}=0\,\text{V}$ for $V_i\gtrsim1.8\,\text{V}$, and the two points where the slope passes through $-1$ are $V_{IL}\approx0.80\,\text{V}$ (upper knee, $V_o\approx2.84\,\text{V}$) and $V_{IH}\approx1.43\,\text{V}$ (lower knee, $V_o\approx0.16\,\text{V}$).
(i) Low noise margin $NM_L$ — slide a straightedge of slope $-1$ along the upper knee; its tangent point gives $V_{IL}$, the largest input still read as LOW, and $NM_L$ is its gap above the guaranteed LOW output of a driving gate:
$$NM_L=V_{IL}-V_{OL}\approx0.80-0=\boxed{0.80\ \text{V}}$$
(ii) High noise margin $NM_H$ — repeat at the lower knee; the slope-$(-1)$ tangent point gives $V_{IH}$, the smallest input read as HIGH, and $NM_H$ is its gap below the guaranteed HIGH output:
$$NM_H=V_{OH}-V_{IH}\approx3.0-1.43=\boxed{1.57\ \text{V}\ (\approx1.6\ \text{V})}$$
(iii) Switching voltage $V_x$ — read where the curve crosses the $45^\circ$ line $V_o=V_i$, directly off the transition:
$$V_x\approx\boxed{1.15\ \text{V}}$$
(iv) Small-signal gain — the inverter biased at $V_x$ is a high-gain amplifier, so its small-signal gain is the slope of the tangent to the VTC at $V_x$. Two points on the straight central segment are $(1.09\,\text{V},\,1.95\,\text{V})$ and $(1.19\,\text{V},\,0.72\,\text{V})$:
$$A_v=\left.\frac{dV_o}{dV_i}\right|_{V_x}\approx\frac{0.72-1.95}{1.19-1.09}\approx\boxed{-12\ \text{V/V}}$$
(Dividing the full output swing by $V_{IH}-V_{IL}$ would give only $-3.0/0.63\approx-4.8$: that is an average slope across both knees, not the small-signal gain at the bias point.)
Part (b) — exact switching voltage. At $V_x$ both transistors are saturated and carry equal current, $I_{Dn}=I_{Dp}$:
$$\frac{k_n}{2}(V_x-V_{tn})^2=\frac{k_p}{2}(V_{DD}-V_x-|V_{tp}|)^2\ \Rightarrow\ \sqrt{\frac{k_n}{k_p}}(V_x-V_{tn})=V_{DD}-V_x-|V_{tp}|$$
With $r=\sqrt{k_n/k_p}=\sqrt{3}=1.732$:
$$V_x(r+1)=V_{DD}-|V_{tp}|+rV_{tn}=3-0.5+1.732(0.4)=3.193$$
$$V_x=\frac{3.193}{1.732+1}=\boxed{1.169\ \text{V}}$$
(Consistent with the graphical estimate of part (a), $V_x\approx1.15\,\text{V}$.)
Part (c) — modifying the circuit for $V_x=1.5\,\text{V}$ ($=V_{DD}/2$). Setting $V_x=1.5\,\text{V}=V_{DD}/2$ in the same relation and solving for the required ratio $r$ gives $r=\sqrt{k_n/k_p}\approx0.91$, i.e. $k_n/k_p\approx0.83$ — nearly matched currents, and in particular a much SMALLER $k_n/k_p$ than the present $3$. Since $k_n=3k_p$ currently biases $V_x$ below $V_{DD}/2$ (the stronger NMOS pulls the switching point down), $V_x$ is raised toward $V_{DD}/2$ by weakening the NMOS relative to the PMOS: increase $(W/L)_p$ (widen the PMOS) or decrease $(W/L)_n$, by roughly the same factor ($\approx3.6\times$) that currently makes $k_n=3k_p$. This is exactly the standard CMOS design rule of sizing the PMOS wider than the NMOS to compensate for the lower hole mobility.
Part (d) — ring-oscillator frequency. An odd number of inverting stages in a closed loop has no stable DC operating point and self-oscillates; each half-cycle requires every one of the $N=5$ stages to switch once, so the period is
$$T=2N\,t_{pd},\qquad t_{pd}=\frac{t_{phl}+t_{plh}}{2}=\frac{1.8+2.2}{2}=2.0\,\text{ns}$$
$$T=2(5)(2.0\,\text{ns})=20\,\text{ns}\ \Rightarrow\ f=\frac{1}{T}=\frac{1}{20\,\text{ns}}=\boxed{50\ \text{MHz}}$$
Check
The part (a) values are read graphically from the printed figure, using its 0.3 V gridlines. The slope passes through $-1$ at $V_i\approx0.80$ and $1.43\,\text{V}$, the curve crosses $V_o=V_i$ at about $1.15\,\text{V}$, and the central tangent slope is about $-12$. Graphical reads like these carry roughly $\pm0.05\,\text{V}$ and $\pm15\%$ uncertainty. The independent analytical switching voltage from part (b), $1.169\,\text{V}$, falls inside that band.
