Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Phys-A5 — Semiconductor Devices & Circuits — National Exams, May 2017
3 hours duration. Closed book exam (useful constants, equations and device models are annexed to the exam paper). Any FIVE (5) of the SEVEN (7) questions constitute a complete exam paper; all seven are answered here as a complete study resource.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (semiconductor/diode physics Ch. 3–4, op-amp and active-filter circuits Ch. 2 & 12, MOSFET small-signal amplifiers Ch. 7, data converters Ch. 17, precision rectifiers Ch. 4); M. M. Mano & M. D. Ciletti, Digital Design, 6th ed. (CMOS logic-family gates Ch. 10); C. Kittel, Introduction to Solid State Physics, 8th ed. (semiconductor carrier transport and statistics Ch. 8).
Given. A 3-stage (resistor ladder → comparator bank → priority encoder + latch) flash ADC. Signal range $0\le S(t)\le3\,\text{V}$.
Symbol
Value
$V_{ref}$ (part b)
3.1 V
Required resolution
≥0.025 V
Comparator delay $t_{c,max}$
1.8 ns
Priority-encoder delay $t_{d,max}$
2 ns
Latch clock-to-output $t_{clk\text{-}Q}$
1.2 ns
Find. (a) ADC type + one advantage/disadvantage; (b) minimum bits $n$; (c) hex code at $S(t)=2\,\text{V}$ ($n=8$); (d) maximum conversion frequency.
[Figure not reproduced: Figure P6 (exam figure). See the official exam paper or the cited reference text.]
Figure P6 — n-bit flash ADC: resistor ladder generates the $m$ reference levels, one comparator per level, a priority encoder + latch produces the final n-bit code.
Approach. (a) identify the topology from the resistor-ladder + one-comparator-per-level structure. (b) the $R/2,R,\dots,R,R/2$ ladder of Figure P6 divides $V_{ref}$ into $m=2^n-1$ equal steps, so $LSB=V_{ref}/(2^n-1)$, with thresholds at $(k-\tfrac12)LSB$; require the LSB to be no coarser than the target resolution and solve for the smallest integer $n$. (c) with $n=8$ fixed, count the thresholds lying below $S(t)$. (d) sum the worst-case delay through every stage in the signal path (comparator → encoder → latch) to get the minimum clock period.
Part (a) — ADC type. This is a flash (parallel) ADC: every one of the $2^n-1$ reference levels has its own dedicated comparator, all firing simultaneously against the same input. Main advantage: it is the fastest ADC architecture — the whole conversion happens in essentially one comparator delay plus encoder/latch delay, with no iterative or successive-approximation steps. Main disadvantage: hardware cost grows exponentially with resolution ($2^n-1$ comparators for $n$ bits), making high-resolution flash ADCs impractically large, power-hungry and expensive.
Part (b) — minimum bits for 0.025 V resolution. The ladder has an $R/2$ at each end and $m-1$ full $R$’s between the $m=2^n-1$ taps, so its total is $mR$ and adjacent thresholds are $LSB=V_{ref}/(2^n-1)$ apart. Requiring this to be no coarser than $0.025\,\text{V}$:
$$2^n-1\ge\frac{V_{ref}}{0.025}=\frac{3.1}{0.025}=124\ \Rightarrow\ 2^n\ge125\ \Rightarrow\ n\ge\log_2(125)=6.97$$
The smallest integer satisfying this is $n=\boxed{7\ \text{bits}}$ (check: $2^7-1=127\ge124$ gives $LSB=3.1/127=24.4\,\text{mV}<25\,\text{mV}$; with $n=6$ the LSB would be $3.1/63=49.2\,\text{mV}$, too coarse).
Part (c) — hex code at $S(t)=2\,\text{V}$, $n=8$. With $n=8$ there are $m=255$ comparators and $LSB=3.1/255=12.157\,\text{mV}$. Comparator $k$ trips at $V_{rk}=(k-\tfrac12)LSB$, and the priority encoder outputs the index of the highest comparator that has tripped, i.e. the number of thresholds below the input:
$$\text{code}=\left\lfloor\frac{S(t)}{LSB}+\frac12\right\rfloor=\left\lfloor\frac{2}{0.012157}+0.5\right\rfloor=\lfloor164.52+0.5\rfloor=165_{10}$$
(Threshold 165 sits at $164.5\times12.157\,\text{mV}=1.9998\,\text{V}$, just below 2 V, and threshold 166 at $165.5\times12.157\,\text{mV}=2.012\,\text{V}$, above it.)
$$165_{10}=10100101_2=\boxed{\text{0xA5}}$$
Part (d) — maximum conversion speed. Each conversion must propagate through the comparator bank, then the priority encoder, then the output latch, in series; the maximum (worst-case) total delay sets the minimum allowable clock period:
$$t_{total}=t_{c,max}+t_{d,max}+t_{clk\text{-}Q}=1.8+2.0+1.2=5.0\,\text{ns}$$
$$f_{max}=\frac{1}{t_{total}}=\frac{1}{5.0\,\text{ns}}=\boxed{200\ \text{MHz}}$$
