Question 4 of 7: Common-Source MOSFET Amplifier — Max-Swing Design
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Comp-A1, Electronics — National Exams, undated sitting (page 1 of the paper reads "May 2018" while every question page reads "May 2019", so the exam period is uncertain). Open-book, 3 hours; the paper's own instructions read "FIVE (5) questions constitute a complete exam paper" while seven distinct 20-mark questions are printed — all seven are answered below as a complete study resource. Where a diode is used without a stated drop, $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode rectifiers/limiters, BJT and MOSFET biasing and small-signal amplifiers, op-amp limiting circuits, CMOS logic gate sizing, R-2R ladder D/A converters) — the single reference text covering every question on this paper.
Given. $v_i$ — $R_{sig}=100\text{k}\Omega$ — $C_{in}$ — gate. Drain: $+10\text{V}$ through $R_D$; source: $-10\text{V}$ through $R_S$. Output at the drain, coupled through $C_{out}$ to $R_L=50\text{k}\Omega$.
Given data
Quantity
Value
$k'_n(W/L)$
$0.5\text{ mA/V}^2$
$V_t$, $V_A$
1V, 50V
Supplies
$+10\text{V}$ (drain), $-10\text{V}$ (source)
$R_{sig}$, $R_L$
$100\text{k}\Omega$, $50\text{k}\Omega$
Target $I_D$, swing
$0.5\text{mA}$, $\pm1\text{V}$ at the drain
Find. $R_S,R_D$; small-signal model parameters; $R_{in}$, $R_o$; overall voltage gain.
Since the gate draws no DC or (ideal) small-signal current, $R_G$'s value does not affect the bias design at all — it only sets $R_{in}$, so it is carried symbolically as $R_{in}=R_G$; the overall gain is reported both as the "core" gain (gate node to output) and with the usual caveat that a gate-bias resistor is normally chosen $\gg R_{sig}$, in which case the input attenuation is negligible.
Approach. DC: $R_G$ fixes $V_G=0\text{V}$ (no gate current), so $V_S=-V_{GS}$ and $R_S$ follows directly; $R_D$ is set by the tightest constraint in the problem — the bottom of the $\pm1\text{V}$ swing must just touch the saturation boundary, which is what makes it the LARGEST allowable $R_D$. AC: standard common-source small-signal model with $g_m,r_o$; $R_{in}=R_G$ (no gate current); $R_o=R_D\|r_o$; gain includes $R_L$ at the output and (if needed) the $R_G/(R_G+R_{sig})$ input divider.
Part (a) — overdrive and $R_S$. $V_{OV}=\sqrt{2I_D/k'_n(W/L)}=\sqrt{2(0.5\text{mA})/0.5\text{mA/V}^2}=\boxed{1.414\text{ V}}\Rightarrow V_{GS}=V_t+V_{OV}=2.414\text{V}$. With $V_G=0$ (via $R_G$, no gate current), $V_S=-V_{GS}=\boxed{-2.414\text{ V}}$. Source loop: $V_S=-10+I_D R_S\Rightarrow R_S=\dfrac{V_S+10}{I_D}=\dfrac{7.586}{0.5\text{mA}}=\boxed{15.17\text{ k}\Omega}$.
Part (a) — largest $R_D$. Saturation requires $V_{DS}\ge V_{OV}$, i.e. $V_D-V_S\ge1.414\text{V}$. The LARGEST $R_D$ places the DC drain voltage exactly high enough that the BOTTOM of the $\pm1\text{V}$ swing sits right at that boundary: $V_{D,DC}-1=V_S+V_{OV}=-1.0\text{V}\Rightarrow V_{D,DC}=\boxed{0.00\text{ V}}$. Then
$$R_D=\frac{10-V_{D,DC}}{I_D}=\frac{10-0}{0.5\text{mA}}=\boxed{20.0\text{ k}\Omega}$$
Part (b) — small-signal parameters. $g_m=2I_D/V_{OV}=2(0.5\text{mA})/1.414\text{V}=\boxed{0.707\text{ mA/V}}$; $r_o=V_A/I_D=50\text{V}/0.5\text{mA}=\boxed{100\text{ k}\Omega}$.
Part (c) — $R_{in}$, $R_o$. The gate draws no current, so $R_{in}=R_G$ (value not stated in the source — see check note). Looking into the drain (before $C_{out}$): $R_o=R_D\|r_o=20\text{k}\|100\text{k}=\boxed{16.67\text{ k}\Omega}$.
Part (d) — voltage gain. With $R_L$ also across the drain in the AC path, $R_D\|r_o\|R_L=20\text{k}\|100\text{k}\|50\text{k}=12.5\text{k}\Omega$, so the gate-to-output ("core") gain is
$$A_{v,\text{core}}=-g_m(R_D\|r_o\|R_L)=-(0.707\text{mA/V})(12.5\text{k}\Omega)=\boxed{-8.84\text{ V/V}}$$
If $R_G\gg R_{sig}=100\text{k}\Omega$ (the usual purpose of a gate-bias resistor), the input divider $R_G/(R_G+R_{sig})\approx1$ and the overall $v_o/v_i\approx-8.84\text{V/V}$; for a stated $R_G$ comparable to $R_{sig}$ this factor would be applied explicitly.
Fig. Q4-b — Small-signal CS equivalent circuit: dependent source $g_m v_{gs}$ from drain to source(ground, AC), with $R_D$, $r_o$, $R_L$ all in parallel at the drain.
