Question 6 of 7: CMOS AND-OR-INVERT (AOI21) Gate — Sizing and Propagation Delay
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Comp-A1, Electronics — National Exams, undated sitting (page 1 of the paper reads "May 2018" while every question page reads "May 2019", so the exam period is uncertain). Open-book, 3 hours; the paper's own instructions read "FIVE (5) questions constitute a complete exam paper" while seven distinct 20-mark questions are printed — all seven are answered below as a complete study resource. Where a diode is used without a stated drop, $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode rectifiers/limiters, BJT and MOSFET biasing and small-signal amplifiers, op-amp limiting circuits, CMOS logic gate sizing, R-2R ladder D/A converters) — the single reference text covering every question on this paper.
Given. Figure 6 is an AND-OR-INVERT 2-1 (AOI21) gate: inputs $A,B$ feed an AND, input $C$ ORs with that result, and the combination is inverted at $Y$.
Given data
Quantity
Value
$C_{ox}$
$1\text{fF}/\mu m^2$
$\mu_n C_{ox}$, $\mu_p C_{ox}$
$50\,\mu A/V^2$, $20\,\mu A/V^2$
$V_{tn}=|V_{tp}|$, $V_{DD}$
1V, 5V
Reference inverter
$L=0.5\mu m$; NMOS $W/L=1.5$; PMOS $W/L=6$
Find. $Y$ (Boolean); the AOI21 transistor-level netlist with sizes matching the reference inverter's worst-case drive; $t_{pLH}$, $t_{pHL}$ driving one reference inverter's gate capacitance.
Approach. Build the pull-down network (PDN) directly from the AOI logic ($AB+C$), then take its series/parallel dual for the pull-up network (PUN). Size every SERIES-connected transistor at twice the reference $W/L$ (so the series pair's halved effective strength still matches the reference) and every stand-alone parallel path at exactly the reference $W/L$; then apply $t_p\approx0.69\,R_{on}C_L$ using the sized worst-case path and the reference inverter's own gate capacitance as the load.
Part (b) — network topology. PDN (pulls $Y$ low when $AB+C$ is true): NMOS $A$ and $B$ in series (implementing $AB$), that series pair in parallel with NMOS $C$ (implementing the OR with $C$). PUN (the series/parallel dual): PMOS $A$ and $B$ in parallel, that combination in series with PMOS $C$ — 3 NMOS + 3 PMOS, 6 transistors total.
Part (b) — NMOS sizing. The series $A$–$B$ path alone must match the reference NMOS strength $(W/L)_{ref}=1.5$ despite being halved by the series connection, so each of $A,B$ is sized at $2\times1.5=\boxed{(W/L)=3.0}$. The single-transistor $C$ path already matches a reference path directly (no series penalty), so $\boxed{(W/L)_C=1.5}$ (unchanged).
Part (b) — PMOS sizing. By the dual logic, a worst-case pull-up path is ONE of $A/B$ in series with $C$; matching the reference $(W/L)_{ref}=6$ through two series transistors requires each of $A,B,C$ at $2\times6=\boxed{(W/L)=12.0}$.
Reference inverter's own capacitance. $W_n=1.5(0.5\mu m)=0.75\mu m$, $W_p=6(0.5\mu m)=3.0\mu m$; its total gate (load) capacitance:
$$C_L=C_{ox}(W_nL+W_pL)=1\text{fF}/\mu m^2\times(0.375+1.5)\mu m^2=\boxed{1.875\text{ fF}}$$
Part (c) — $t_{pLH}$. Uses the sized PMOS worst-case path (effective $W/L=6$, matching the reference by design):
$$R_{on,p}=\frac{1}{\mu_p C_{ox}(W/L)(V_{DD}-|V_{tp}|)}=\frac{1}{20\mu A/V^2\times6\times4\text{V}}=\boxed{2083\,\Omega}$$
$$t_{pLH}=0.69\,R_{on,p}C_L=0.69(2083)(1.875\text{fF})=\boxed{2.70\text{ ps}}$$
Part (d) — $t_{pHL}$. Uses the sized NMOS worst-case path (effective $W/L=1.5$):
$$R_{on,n}=\frac{1}{\mu_n C_{ox}(W/L)(V_{DD}-V_{tn})}=\frac{1}{50\mu A/V^2\times1.5\times4\text{V}}=\boxed{3333\,\Omega}$$
$$t_{pHL}=0.69\,R_{on,n}C_L=0.69(3333)(1.875\text{fF})=\boxed{4.31\text{ ps}}$$
Fig. Q6-b — AOI21 transistor-level netlist: PMOS $A\|B$ in series with $C$ (pull-up), NMOS $A$-series-$B$ in parallel with $C$ (pull-down), each sized to match the reference inverter's worst-case drive.
