Question 5 of 7: DC Restorer (Clamper) Driving a Voltage Follower — Steady State at $v_{in}=0$
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Comp-A1, Electronics — National Exams, undated sitting (page 1 of the paper reads "May 2018" while every question page reads "May 2019", so the exam period is uncertain). Open-book, 3 hours; the paper's own instructions read "FIVE (5) questions constitute a complete exam paper" while seven distinct 20-mark questions are printed — all seven are answered below as a complete study resource. Where a diode is used without a stated drop, $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode rectifiers/limiters, BJT and MOSFET biasing and small-signal amplifiers, op-amp limiting circuits, CMOS logic gate sizing, R-2R ladder D/A converters) — the single reference text covering every question on this paper.
Question 5: DC Restorer (Clamper) Driving a Voltage Follower — Steady State at $v_{in}=0$ (20 marks)
Given. Series capacitor $C$ from $v_{in}$ to node $A$; diode $D_1$ (anode at $A$, cathode at ground) shunts $A$; node $A$ drives the op-amp's non-inverting input; the op-amp is wired as a unity-gain follower (output tied to the inverting input), output node $B=V_{out}$, with $R_L=1\text{k}\Omega$ from $B$ to ground. $V_{ref}=0\text{V}$; supplies $\pm12\text{V}$; $V_F=0.7\text{V}$.
Find. The steady-state $V_{out}$ for $v_{in}=0$ with a physical explanation; sketches of $V_{out}(t)$, $V_A(t)$, $V_B(t)$.
Check — engineering assumption
The source states $v_{in}=0$ for BOTH sub-parts, which is unusual for a DC-restorer question. Solved literally as given below; the concept aside separately summarizes how the SAME circuit clamps a genuine periodic input, since that is very likely the intended full picture.
Approach. A clamper's output level is set entirely by the charge parked on its series capacitor, and that charge only changes when the input has enough $dV/dt$ to forward-bias the clamp diode. A literally constant input provides no such event.
Explain (part a). Because $v_{in}(t)\equiv0$ for all $t$, $dv_{in}/dt=0$ everywhere, so no displacement current ever flows through $C$ and $D_1$ never experiences a forward-bias event. With no charging path ever activated, the capacitor holds whatever charge it started with — zero, for a circuit beginning from rest — and the "restorer" simply never restores anything, because there is no waveform edge for it to act on.
Calculate (part a). With zero charge on $C$, node $A$ sits at the same potential as $v_{in}$ straight through the (uncharged) capacitor: $V_A=v_{in}=\boxed{0\text{ V}}$ for all $t$. The op-amp follower forces $V_{out}=V_B=V_A=\boxed{0\text{ V}}$ for all $t$ as well. Consistency check: $D_1$ (anode at $A=0\text{V}$, cathode at ground $=0\text{V}$) sits at exactly zero net forward bias, consistent with carrying zero current at every instant — a self-consistent equilibrium.
Sketch (part b). $V_A(t)$, $V_B(t)$, and $V_{out}(t)$ are all flat lines at $0\text{V}$ for all $t$ (Fig. Q5) — there are no peak, period, or transition values to mark, since nothing in the circuit ever moves away from its zero-charge, zero-current starting point.
Fig. Q5 — $V_A$, $V_B$, $V_{out}$ all coincide at a flat $0\text{V}$ line: with $v_{in}\equiv0$, the clamper never has an event to charge its capacitor.