Question 7 of 7: 6-Bit R-2R Ladder DAC

Question 7: 6-Bit R-2R Ladder DAC (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A 6-bit R-2R ladder: 6 series-$R$/shunt-$2R$ stages (switches $S_5,S_4,S_3,S_2,S_1,S_0$, MSB to LSB) fed from $V_{ref}$, terminated by an extra $2R$ to ground at the far end; each switch routes its rung either to the summing bus (virtual ground) or to real ground. A feedback resistor, also $R$, closes an inverting op-amp whose $-$ input is the bus and $+$ input is grounded.

Find. Switch currents for $S=111111$ and $S=000000$; $V_{out}$ for $S=001001$; an alternative DAC architecture.

Approach. Both switch destinations (the bus and real ground) sit at $0\text{V}$, so the ladder's internal current distribution is completely independent of the switch pattern — solve it ONCE by nodal reduction from the terminating $2R$ backward (the classic R-2R identity: looking right from any node the resistance to $0\text{V}$ is always $R$), then get $V_{out}$ for any code from $-R_F$ times the sum of whichever rung currents are routed to the bus.

1. R-2R self-similarity. Looking right from any internal node, the shunt $2R$ (switch) in parallel with (series $R$ + look-right resistance of the next stage) always reduces to exactly $R$ — confirmed stage-by-stage starting from the terminating $2R\|2R=R$ at the far end and working backward, since $2R\|(R+R)=R$ at every stage. Because the shunt leg ($2R$) and the continuing leg ($R+R=2R$) are therefore EQUAL at every node, current entering a node splits exactly in half between "down the switch" and "onward to the next stage."
2. First-stage current. $V_{ref}$ sees its own series $R$ plus the whole ladder's look-in resistance $R$, i.e. $2R$ total: $I_{in}(S_5\text{ node})=V_{ref}/2R=2.5\text{V}/20\text{k}\Omega=125\,\mu A$. Half of that goes down the $S_5$ switch: $I(S_5)=\boxed{62.5\,\mu A}$.
3. Binary halving. Each successive stage's switch current is exactly half the previous one (same argument applied node-by-node): $I(S_4)=31.25\,\mu A$, $I(S_3)=15.625\,\mu A$, $I(S_2)=7.8125\,\mu A$, $I(S_1)=3.90625\,\mu A$, $I(S_0)=1.953125\,\mu A$ — the boxed answer to part (a) ($S=111111$): every switch's current is fixed by the ladder alone, independent of the code.
4. Part (b), $S=000000$. Identical currents to step 3 still flow in every rung (the ladder cannot distinguish "bus" from "ground" — both are $0\text{V}$); the only change is that NONE of that current reaches the summing bus, so $\boxed{V_{out}=0\text{V}}$ even though the internal ladder currents are numerically unchanged from part (a).
5. Part (c), $S=(001001)=(S_5S_4S_3S_2S_1S_0)=(0,0,1,0,0,1)$. Only $S_3$ and $S_0$ route their currents to the bus: $I_{out}=I(S_3)+I(S_0)=15.625+1.953125=17.578125\,\mu A$. $$V_{out}=-R_F\,I_{out}=-10\text{k}\Omega\times17.578\,\mu A=\boxed{-0.1758\text{ V}}$$ Check via the closed form for this ladder, $V_{out}=-V_{ref}\,D/128$ with $D=001001_2=9$: $V_{out}=-2.5(9)/128=-0.1758\text{V}$ — matches.
6. Part (d) — alternative architecture. A binary-weighted-resistor summing DAC performs the same conversion with a single op-amp summing junction and $N$ input resistors $R,2R,4R,\ldots,2^{N-1}R$ (one per bit, each switched to $V_{ref}$ or ground), giving $V_{out}=-R_F V_{ref}\sum b_i/2^iR_i$-style weighting directly. It needs only conceptually simple per-bit weighting, but the resistor spread grows as $2^N$ (a 6-bit version needs values from $R$ to $32R$), which is far harder to fabricate and trim precisely than the R-2R ladder's two-value ($R$, $2R$) design — exactly why R-2R ladders dominate in practice.