Question 6 of 7: CMOS 3-Input NOR/NAND Gate Sizing

Question 6: CMOS 3-Input NOR/NAND Gate Sizing (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Reference symmetric inverter (same technology, same $L=0.5\,\mu\text{m}$): $(W/L)_{n,\text{ref}}=1.5$, $(W/L)_{p,\text{ref}}=6$.

Find. NOR3/NAND3 Boolean expressions and transistor-level schematics; per-transistor $(W/L)$ to match the inverter's drive; for the NAND3, the ratio of maximum to minimum available charge/discharge current.

Approach. A CMOS gate's pull-down (NMOS) network mirrors the AND/OR structure directly and its pull-up (PMOS) network is the series/parallel dual; a single transistor matches the reference inverter's drive only if it is never forced into a series chain — a transistor that is one of $k$ in series (the network's worst case) must be sized $k\times$ wider to deliver the same drive as a lone reference device.

1. Part (a) — NOR3. $F=\overline{A+B+C}$. Pull-down (NMOS): $A$, $B$, $C$ each in a separate branch, all three branches in parallel from $F$ to ground (any one input high pulls $F$ low). Pull-up (PMOS): $A$, $B$, $C$ in series from $V_{DD}$ to $F$ (all three inputs must be low simultaneously to pull $F$ high) — the standard series/parallel dual (Fig. Q6(a)).
2. Part (b) — NOR3 sizing. NMOS worst case is a single transistor conducting alone (parallel network, one input high) — identical to the lone reference inverter, so no resizing needed: $$(W/L)_{n,\text{NOR}}=\boxed{1.5}\text{ (each of the 3 NMOS)}$$ PMOS worst case is all three in series conducting together (the only way to pull up, since all inputs must be low) — three series devices of the reference width would have $3\times$ the ON-resistance of one, so each must be $3\times$ wider to restore the reference drive: $$(W/L)_{p,\text{NOR}}=3\times6=\boxed{18}\text{ (each of the 3 PMOS)}$$
3. Part (c) — NAND3 (structure and sizing). $F=\overline{ABC}$. Pull-down (NMOS): $A,B,C$ in series (all three must be high to pull $F$ low). Pull-up (PMOS): $A,B,C$ in parallel (any one input low pulls $F$ high) — the dual of NOR3 (Fig. Q6(b)). By the identical series/parallel sizing argument (this time NMOS is the series network, PMOS the parallel one): $$(W/L)_{n,\text{NAND}}=3\times1.5=\boxed{4.5}\text{ (each of the 3 NMOS, series)}$$ $$(W/L)_{p,\text{NAND}}=\boxed{6}\text{ (each of the 3 PMOS, parallel — unchanged from the reference)}$$
4. Part (d) — max/min available current ratio (NAND3). The series NMOS pull-down conducts (nonzero current) only in the single state where all three are on ($A=B=C=1$) — by design (Part (c)'s $3\times$ sizing) this exactly matches the reference inverter's drive, i.e. $1\times$. The parallel PMOS pull-up conducts in every other input combination, contributing $1\times,2\times,$ or $3\times$ the reference drive depending on how many of $A,B,C$ are low (1, 2, or 3 respectively): $$I_{\max}=3\times I_{\text{ref}}\quad(A=B=C=0\text{, all 3 PMOS on in parallel})$$ $$I_{\min}=1\times I_{\text{ref}}\quad(\text{exactly one PMOS on, or the series NMOS all-on case})$$ $$\frac{I_{\max}}{I_{\min}}=\boxed{3:1}$$