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22-Elec-A4 Digital Systems and Computers: December 2019

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Boolean minimization and hazards
  2. Question 2 Function realization — gates, MUX, decoder
  3. Question 3 Analysis of a two-RS-flip-flop circuit
  4. Question 4 HC11 address-decoded I/O routing
  5. Question 5 Serial character echo with case swap; TxD waveforms
  6. Question 6 Parallel I/O — CPU methods and device handshaking

Start with Question 1 →

National Exams — December 2019 · 16-Elec-A4 Digital Systems & Computers. Closed book · 3 hours · one of two approved calculators. Six questions; any five constitute a complete paper and all questions are worth 12 marks. All six are solved here as a study resource.

Reference texts: M. M. Mano & M. D. Ciletti, Digital Design (6th ed.); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.); R. J. Tocci, N. S. Widmer & G. L. Moss, Digital Systems: Principles and Applications (12th ed.); Motorola/Freescale M68HC11 Reference Manual; V. C. Hamacher, Z. G. Vranesic & S. G. Zaky, Computer Organization (5th ed.).

Check — figure readings. The two circuit figures are redrawn below from the printed paper. Readings used below: Q1’s second and fifth product terms are $A\overline{B}C$ and $\overline{A}\,\overline{B}C\overline{D}$; Q2(a) asks for 8:1-multiplexer realizations and gives $ABC=011$ and $111$ as don’t-cares for $f_1$; Q3’s gates are three-input ANDs and flip-flop $B$ is wired as a toggle ($R_B=B$, $S_B=\overline{B}$), so the circuit is a binary up/down counter; Q4’s flip-flop clock is taken from decoder output ̅Y2 (third output down), not ̅Y0. Each correction is explained in the relevant answer.