22-Elec-A4 Digital Systems and Computers · December 2019
Question 2 of 6: Function realization — gates, MUX, decoder
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — December 2019 · 16-Elec-A4 Digital Systems & Computers.
Closed book · 3 hours · one of two approved calculators. Six questions; any five constitute a complete paper and all questions are worth 12 marks. All six are solved here as a study resource.
Reference texts: M. M. Mano & M. D. Ciletti, Digital Design (6th ed.); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.); R. J. Tocci, N. S. Widmer & G. L. Moss, Digital Systems: Principles and Applications (12th ed.); Motorola/Freescale M68HC11 Reference Manual; V. C. Hamacher, Z. G. Vranesic & S. G. Zaky, Computer Organization (5th ed.).
Check — figure readings. The two circuit figures are redrawn below from the printed paper. Readings used below: Q1’s second and fifth product terms are $A\overline{B}C$ and $\overline{A}\,\overline{B}C\overline{D}$; Q2(a) asks for 8:1-multiplexer realizations and gives $ABC=011$ and $111$ as don’t-cares for $f_1$; Q3’s gates are three-input ANDs and flip-flop $B$ is wired as a toggle ($R_B=B$, $S_B=\overline{B}$), so the circuit is a binary up/down counter; Q4’s flip-flop clock is taken from decoder output ̅Y2 (third output down), not ̅Y0. Each correction is explained in the relevant answer.
Question 2: Function realization — gates, MUX, decoder (12 marks)
Given. Three-variable functions specified by minterm/maxterm lists and by algebraic form; for $f_1$ the combinations $ABC=011$ (m3) and $111$ (m7) are don’t-cares.
Find. 8:1-MUX realizations for part (a), 4:1-MUX realizations for part (b), and a shared 3:8-decoder + OR realization for part (c).
Approach. An 8:1 MUX with $ABC$ on its select lines reproduces the truth table directly (data input $I_k$ = value of minterm $k$, don’t-cares free to tie either way); for the 4:1 MUX use two variables as the select lines and express the residue on the third variable as each data input; for the decoder, a 3:8 decoder generates every minterm, so each output function is simply the OR of its minterms.
Part (a), 8:1 MUX. Connect $S_2S_1S_0=A\,B\,C$ on each MUX and tie data input $I_k$ to the function value on row $k$. For $f_1=\Sigma m(1,4,6)$ with don’t-cares m3, m7: $I_1=I_4=I_6=1$, $I_0=I_2=I_5=0$, and $I_3,I_7$ may be tied to either rail (tie them to 0). For $f_2=\Pi M(0,1,2,5)$ the maxterm indices are the zeros, so the ones are m3, m4, m6, m7: $I_3=I_4=I_6=I_7=1$, $I_0=I_1=I_2=I_5=0$.
8:1 MUX data inputs (select $S_2S_1S_0=ABC$; X = don’t-care)
Function
$I_0$
$I_1$
$I_2$
$I_3$
$I_4$
$I_5$
$I_6$
$I_7$
$f_1$
0
1
0
X (0)
1
0
1
X (0)
$f_2$
0
0
0
1
1
0
1
1
$$\boxed{f_1:\;(I_0,\dots,I_7)=(0,1,0,X,1,0,1,X),\qquad f_2:\;(I_0,\dots,I_7)=(0,0,0,1,1,0,1,1)}$$
For reference, the minimal gate forms are $f_2=A\overline{C}+BC$ and, taking don’t-care m3 as 1 so that m1 and m3 merge, $f_1=A\overline{C}+\overline{A}C=A\oplus C$ (without the don’t-cares it would be $A\overline{C}+\overline{A}\,\overline{B}C$).
Part (b), 4:1 MUX. Take the select lines $S_1S_0 = A\,B$ and reduce each function to a residue in $C$ per select address:
MUX data-input residues (select = $AB$)
$AB$
$I$
$f_1$ data
$f_2$ data
00
$I_0$
$C$
$0$
01
$I_1$
$0$
$C$
10
$I_2$
$\overline{C}$
$\overline{C}$
11
$I_3$
$\overline{C}$
$1$
Each MUX needs only $C$ and $\overline{C}$ (one inverter) at its data inputs. For $f_1$ the don’t-cares sit at $AB=01$ (m3) and $AB=11$ (m7); the residues above take both as 0, which is valid. Using them instead (m3 = 1, m7 = 0) gives $I_1=C$ and the data word $(C,\,C,\,\overline{C},\,\overline{C})$, i.e. $f_1=A\oplus C$ with $B$ unused — an equally correct and more regular alternative.
Part (c), 3:8 decoder + OR. Drive the decoder address with $A_2A_1A_0=A\,B\,C$. Expand each function to minterms: $f_1=A(\overline{B}+C)=\Sigma m(4,5,7)$; $f_2=\Sigma m(0,3,4)$; $f_3=ABC+B\overline{C}=\Sigma m(2,6,7)$. Each output is the OR of its active-high decoder lines:
$$\boxed{f_1=Y_4{+}Y_5{+}Y_7,\quad f_2=Y_0{+}Y_3{+}Y_4,\quad f_3=Y_2{+}Y_6{+}Y_7}$$
Figure 2.1 — $f_1$ on a 4:1 MUX, select $=AB$, data $=(C,0,\overline{C},\overline{C})$.
Figure 2.2 — $f_2$ on a 4:1 MUX, select $=AB$, data $=(0,C,\overline{C},1)$.
Figure 2.3 — the three functions of part (c) from one 3:8 decoder (inputs $A,B,C$) and three OR gates.
Question 2 results
Item
Realization
(a)(i) $f_1$, 8:1 MUX
sel $ABC$; $I_{0..7}=(0,1,0,X,1,0,1,X)$
(a)(ii) $f_2$, 8:1 MUX
sel $ABC$; $I_{0..7}=(0,0,0,1,1,0,1,1)$
(b) MUX $f_1$
sel $AB$; $I_0{=}C,I_1{=}0,I_2{=}\overline{C},I_3{=}\overline{C}$
(b) MUX $f_2$
sel $AB$; $I_0{=}0,I_1{=}C,I_2{=}\overline{C},I_3{=}1$