HC11 address-decoded I/O routing: 22-Elec-A4 Digital Systems and Computers, December 2019, Q4

Question 4: HC11 address-decoded I/O routing (12 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Decoder address $A_2A_1A_0 = A_{15}A_{14}A_{13}$; the flip-flop is clocked by a decoder output (read from the drawing as $\overline{Y}_2$); on that clock it latches $D_0$; $Q=1$ closes switch 1 (→ HOST), $Q=0$ (so $\overline{Q}=1$) closes switch 2 (→ MCU).

Find. The effect of each of the four store operations.

Check — clock source. The clock tap leaves the decoder’s third output, $\overline{Y}_2$. With $\overline{Y}_2$ the four parts give distinct, sensible answers; with $\overline{Y}_0$ all four would be “No Action”. The answer follows the drawing ($\overline{Y}_2$).

Approach. A store only reprograms the latch if its address activates $\overline{Y}_2$, i.e. $A_{15}A_{14}A_{13}=010$ (any address in the $4000_{16}$–$5\text{FFF}_{16}$ block). When it does, the latched $D_0$ (bit 0 of the stored byte) picks the route; otherwise the routing is unchanged.

Decode each store address. Take the top three address bits: $8000_{16}\Rightarrow100=Y_4$; $4000_{16}\Rightarrow010=Y_2$; $5000_{16}\Rightarrow010=Y_2$; $2500_{16}\Rightarrow001=Y_1$. Only (b) and (c) hit $\overline{Y}_2$ and clock the flip-flop.
Read $D_0$ where the clock fires. $D_0=\text{bit }0$ of the accumulator value: $29_{16}=0010\,1001\Rightarrow D_0=1$; $B4_{16}=1011\,0100\Rightarrow D_0=0$.
Apply the routing rule. $$\boxed{\text{(a) No Action}\quad\text{(b) HOST}\quad\text{(c) MCU}\quad\text{(d) No Action}}$$ (b): $Q\!\leftarrow\!1\Rightarrow$ switch 1 closes → HOST. (c): $Q\!\leftarrow\!0\Rightarrow$ switch 2 closes → MCU. (a),(d): decoder selects $Y_4/Y_1$, $\overline{Y}_2$ never pulses, so the previously latched route is untouched.

Figure 4.1 — per-instruction decode. The stored byte’s $D_0$ only reaches the latch when $A_{15}A_{14}A_{13}=010$.

Question 4 results
Instruction	$A_{15}A_{14}A_{13}$	Line	$D_0$	Result
(a) staa $8000_{16}$	100	$Y_4$	—	No Action
(b) staa $4000_{16}$	010	$Y_2$	1	HOST port
(c) staa $5000_{16}$	010	$Y_2$	0	MCU port
(d) staa $2500_{16}$	001	$Y_1$	—	No Action

Topic. Memory-mapped I/O and partial address decoding on the 68HC11.

Key relations. A store to any address in the decoded block strobes the selected active-low output for one cycle; only the decoded address bits matter, so the low-order bits ($A_{12}\!-\!A_0$) and the byte value (except $D_0$) are don’t-cares here.

Why this works. The decoder converts an address region into a one-cycle clock pulse; the rising edge as $\overline{Y}_2$ returns to ‘1’ latches $D_0$ into the D flip-flop, whose $Q/\overline{Q}$ statically hold the routing until the next write into that region. This is the standard “write a control bit to a mapped port” idiom.

Common pitfall. Assuming the byte value or the low address bits matter: only $A_{15}A_{14}A_{13}$ select the port and only $D_0$ is latched. Writing to a non-selected block (parts a, d) changes nothing.

Source. Motorola M68HC11 Reference Manual (address decoding, memory-mapped I/O); Hamacher et al., Computer Organization, §7 (I/O interfacing).

Question 4 of 6: HC11 address-decoded I/O routing

Question 4: HC11 address-decoded I/O routing (12 marks)