22-Elec-A4 Digital Systems and Computers · December 2019
Question 3 of 6: Analysis of a two-RS-flip-flop circuit
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — December 2019 · 16-Elec-A4 Digital Systems & Computers.
Closed book · 3 hours · one of two approved calculators. Six questions; any five constitute a complete paper and all questions are worth 12 marks. All six are solved here as a study resource.
Reference texts: M. M. Mano & M. D. Ciletti, Digital Design (6th ed.); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.); R. J. Tocci, N. S. Widmer & G. L. Moss, Digital Systems: Principles and Applications (12th ed.); Motorola/Freescale M68HC11 Reference Manual; V. C. Hamacher, Z. G. Vranesic & S. G. Zaky, Computer Organization (5th ed.).
Check — figure readings. The two circuit figures are redrawn below from the printed paper. Readings used below: Q1’s second and fifth product terms are $A\overline{B}C$ and $\overline{A}\,\overline{B}C\overline{D}$; Q2(a) asks for 8:1-multiplexer realizations and gives $ABC=011$ and $111$ as don’t-cares for $f_1$; Q3’s gates are three-input ANDs and flip-flop $B$ is wired as a toggle ($R_B=B$, $S_B=\overline{B}$), so the circuit is a binary up/down counter; Q4’s flip-flop clock is taken from decoder output ̅Y2 (third output down), not ̅Y0. Each correction is explained in the relevant answer.
Question 3: Analysis of a two-RS-flip-flop circuit (12 marks)
Given. From the printed schematic: $X$ passes through an inverter (so both $X$ and $\overline{X}$ are available); four three-input AND gates feed two OR gates, whose outputs drive $R_A$ (upper OR) and $S_A$ (lower OR). Tracing the input rails: AND1 $=\overline{X}AB$, AND2 $=XA\overline{B}$, AND3 $=\overline{X}\,\overline{A}B$, AND4 $=X\overline{A}\,\overline{B}$. Flip-flop $B$ has no gate: its $R_B$ pin is tied (junction dot) to its own $Q$ output $B$, and $S_B$ to its own $\overline{Q}$ output $\overline{B}$; the same $B$ and $\overline{B}$ rails continue left into the AND gates.
Find. The four input equations, the state table $\{A,B,X\}\to\{A^+,B^+\}$, and the state diagram.
Check — figure read from the printed figure. The page actually prints an inverter on $X$, three-input ANDs and two OR gates that drive only $R_A$ and $S_A$, while $R_B$ and $S_B$ are wired straight back to $B$ and $\overline{B}$. The equations below follow the printed drawing; every flip-flop input then has exactly one driver and $R\cdot S=0$ holds on both flip-flops, which confirms the trace.
Approach. Read the gate network into $R,S$ equations; apply the clocked-RS next-state law $Q^+ = S + \overline{R}\,Q$ (with $R\!\cdot\!S=0$) to each flip-flop; tabulate and draw.
Input equations (part a). OR-ing the AND terms that feed each input:
$$\boxed{\begin{aligned}
R_A &= \overline{X}AB + XA\overline{B} = A\,(X\oplus B), & S_A &= \overline{X}\,\overline{A}B + X\overline{A}\,\overline{B} = \overline{A}\,(X\oplus B)\\
R_B &= B, & S_B &= \overline{B}
\end{aligned}}$$
$R_A S_A$ contains $A\overline{A}=0$ and $R_B S_B = B\overline{B}=0$, so no forbidden input occurs.
Next-state law. Both cells have the RS-as-T form $R=Q\,T$, $S=\overline{Q}\,T$. With $T_A = X\oplus B$: $A^+ = S_A + \overline{R_A}A = \overline{A}T_A + A\overline{T_A} = A\oplus T_A$. For $B$: $B^+ = S_B + \overline{R_B}B = \overline{B} + \overline{B}B = \overline{B}$ (an unconditional toggle, $T_B=1$). Thus
$$\boxed{A^+ = A \oplus X \oplus B,\qquad B^+ = \overline{B}}$$
State transition table (part b).
State table — present $(A,B)$, input $X$, next $(A^+,B^+)$
A B
X=0 → A⁺B⁺
X=1 → A⁺B⁺
0 0
0 1
1 1
0 1
1 0
0 0
1 0
1 1
0 1
1 1
0 0
1 0
For $X=0$ the states count up $00\to01\to10\to11\to00$; for $X=1$ they count down $00\to11\to10\to01\to00$.
Interpretation. This is a 2-bit synchronous binary up/down counter: $B$ is the LSB and toggles every clock, and $A$ toggles when $B=1$ while counting up ($X=0$) or when $B=0$ while counting down ($X=1$). $X$ is the direction control; all four states are used, so there are no unused states and the counter is inherently self-correcting.
Figure 3.1 — state diagram. Blue ($X{=}0$) counts up $00 o01 o10 o11$, red ($X{=}1$) counts down.
