Question 1 of 5: Common-Source MOSFET Amplifier — Bias Design and Gain
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — May 2017 · 16-Elec-A5, Electronics. Closed-book, 3 hours; answer all FIVE questions (20 marks each). Op-amps ideal, supplies ±15 V (Note 7).
Reference texts (22-Elec-A5 Electronics):
A. S. Sedra & K. C. Smith, Microelectronic Circuits, 7th/8th ed. — Ch. 4 (diodes, clippers & clampers), Ch. 5–7 (MOSFET/BJT biasing & small-signal amplifiers), Ch. 2 (op-amp circuits).
R. C. Jaeger & T. N. Blalock, Microelectronic Circuit Design, 5th ed. — single-stage amplifier design and DC bias.
Boylestad & Nashelsky, Electronic Devices and Circuit Theory — diode wave-shaping (clampers/DC restorers).
Check — drawing readings. Two readings of the printed schematics drive the answers: (Q1) the MOSFET source resistor $R_S$ has no bypass capacitor — the stage is a common-source amplifier with source degeneration. (Q4) the second transistor $Q_2$ is a PNP (emitter tied through $R_{E2}$ to $V_{CC}$, collector through $R_{C2}$ to ground), not an NPN.
Question 1: Common-Source MOSFET Amplifier — Bias Design and Gain (20 marks)
Given. An n-channel MOSFET common-source stage biased in saturation, driven from a source $v_1$ through $R_i$ and coupled by $C_1$; the drain drives $R_L$ through $C_2$. The source resistor $R_S$ is unbypassed.
Given data
Quantity
Value
Quantity
Value
$V_{TH}$
1 V
$V_{DD}$
15 V
$K$
4 mA/V$^2$
$I_D$
0.5 mA
$\lambda$
0
$V_S,\ V_D$
3.5 V, 6 V
$R_{in}$
1.67 MΩ
$R_i$
100 kΩ
$R_L$
200 kΩ
Find. (a) the four bias resistors $R_{G1},R_{G2},R_S,R_D$; (b) the overall small-signal gain from the source $v_1$ to $v_{out}$.
[Figure not reproduced: circuit. See the official exam paper or the cited reference text.]
Figure 1.1 — Common-source stage (redrawn from the exam). The source resistor $R_S$ carries no bypass capacitor, so it degenerates the AC gain.
Approach. Set the DC operating point from the saturation square-law and Ohm’s law across each resistor, then size the gate divider for the required $V_G$ and the specified input resistance; for (b) build the small-signal model with $r_o=\infty$ (since $\lambda=0$) and an unbypassed source.
Overdrive and $V_{GS}$ from the saturation law. With $I_D=\tfrac12 K (V_{GS}-V_{TH})^2$, $\ (V_{GS}-V_{TH})=\sqrt{2I_D/K}=\sqrt{2(0.5)/4}=0.5$ V, so $V_{GS}=1.5$ V.
Drain resistor. The drain drops $V_{DD}-V_D=9$ V, so $R_D=\dfrac{V_{DD}-V_D}{I_D}=\dfrac{9}{0.5\ \text{mA}}=18\ \text{k}\Omega.$
Gate divider. $V_G=V_{GS}+V_S=1.5+3.5=5$ V. The MOSFET gate draws no current, so $V_G=V_{DD}\dfrac{R_{G2}}{R_{G1}+R_{G2}}=5\Rightarrow R_{G1}=2R_{G2}$, and $R_{in}=R_{G1}\Vert R_{G2}=1.67\ \text{M}\Omega\Rightarrow \tfrac23 R_{G2}=1.67\ \text{M}\Omega.$ Hence $\boxed{R_{G1}=5\ \text{M}\Omega,\ \ R_{G2}=2.5\ \text{M}\Omega,\ \ R_S=7\ \text{k}\Omega,\ \ R_D=18\ \text{k}\Omega}$.
Confirm saturation. $V_{DS}=V_D-V_S=2.5$ V, which is greater than the overdrive $V_{GS}-V_{TH}=0.5$ V, so $M_1$ is indeed saturated — the square-law design is consistent.
Loaded stage gain with an unbypassed source. The AC drain load is $R_D\Vert R_L=18\Vert200=16.5\ \text{k}\Omega$. With $r_o=\infty$ and $R_S$ unbypassed, $A_{v,\text{stage}}=\dfrac{v_{out}}{v_g}=\dfrac{-g_m(R_D\Vert R_L)}{1+g_m R_S}=\dfrac{-(2\ \text{mA/V})(16.5\ \text{k}\Omega)}{1+(2)(7)}=\dfrac{-33.0}{15}=-2.20.$
Input attenuation. Between $v_1$ and the gate, $R_i$ and $R_{in}$ divide: $\dfrac{v_{in}}{v_1}=\dfrac{R_{in}}{R_{in}+R_i}=\dfrac{1.67}{1.77}=0.943.$
Check — source degeneration. The schematic shows no capacitor across $R_S$, so the loop gain is set by $g_m R_S=14$ and the gain collapses to $\approx-2.2$ (essentially $-R_D\Vert R_L/R_S$). Had a bypass capacitor been intended, the stage gain would instead be $-g_m(R_D\Vert R_L)=-33$ and the overall gain $\approx-31$ V/V.
