22-Elec-A5 Electronics · May 2017

Question 5 of 5: Diode Wave-Shaping — Five Clamper Circuits

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

National Exams — May 2017 · 16-Elec-A5, Electronics. Closed-book, 3 hours; answer all FIVE questions (20 marks each). Op-amps ideal, supplies ±15 V (Note 7).

Reference texts (22-Elec-A5 Electronics):

A. S. Sedra & K. C. Smith, Microelectronic Circuits, 7th/8th ed. — Ch. 4 (diodes, clippers & clampers), Ch. 5–7 (MOSFET/BJT biasing & small-signal amplifiers), Ch. 2 (op-amp circuits).
R. C. Jaeger & T. N. Blalock, Microelectronic Circuit Design, 5th ed. — single-stage amplifier design and DC bias.
Boylestad & Nashelsky, Electronic Devices and Circuit Theory — diode wave-shaping (clampers/DC restorers).

Check — drawing readings. Two readings of the printed schematics drive the answers: (Q1) the MOSFET source resistor $R_S$ has no bypass capacitor — the stage is a common-source amplifier with source degeneration. (Q4) the second transistor $Q_2$ is a PNP (emitter tied through $R_{E2}$ to $V_{CC}$, collector through $R_{C2}$ to ground), not an NPN.

Question 5: Diode Wave-Shaping — Five Clamper Circuits (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Each circuit couples $v_I$ through a series capacitor $C$ to the output node $v_O$, which is loaded by a diode/resistor network to ground. Input: $\pm10$ V square wave; $V_\gamma=0.7$ V; $RC\gg T$ (the capacitor voltage is essentially constant over a period).

Find. the steady-state output waveform (its two levels) for each of (a)–(e).

[Figure not reproduced: circuit. See the official exam paper or the cited reference text.]

Figure 5.1 — The five circuits (a)–(e), redrawn from the exam.

[Figure not reproduced: circuit. See the official exam paper or the cited reference text.]

Figure 5.2 — Input $v_I$: a $\pm10$ V square wave, half-period $T$.

Approach. Each is a clamper (DC restorer): the series $C$ blocks DC and settles to a constant $V_C$ so that $v_O=v_I-V_C$. Since $RC\gg T$, $V_C$ barely changes within a period, so the output is a square wave whose two flat levels follow from a charge-balance condition — the average current into $C$ over one full period is zero.

(a) Single diode (anode at $v_O$) in series with $R$. When $v_O$ tries to go positive the diode conducts and charges $C$; when $v_O$ is negative the diode blocks and, since $R$ is in series with it, there is no discharge path — a perfect clamp. The positive peak is pinned at $+0.7$ V, so $V_C=10-0.7=9.3$ V and $\boxed{v_O:\ +0.7\ \text{V (high)},\ -19.3\ \text{V (low)}}$ (negative clamp).
(b) Anti-parallel diodes, each with $2R$. The network is symmetric, so charge balance gives $v_{O,\text{hi}}+v_{O,\text{lo}}=0\Rightarrow V_C=0$. The output is essentially the input, $\boxed{v_O:\ +10\ \text{V}/-10\ \text{V}}$ — a symmetric network produces no DC restoration (the $2R$ branches only carry small balancing currents).
(c) Diode+$R$ (anode at $v_O$) in parallel with a plain $R$ to ground. The plain $R$ conducts every half-cycle; charge balance $2v_{O,\text{hi}}-0.7+v_{O,\text{lo}}=0$ with $v_{O,\text{hi}}=10-V_C$, $v_{O,\text{lo}}=-10-V_C$ gives $V_C=3.1$ V, so $\boxed{v_O:\ +6.9\ \text{V}/-13.1\ \text{V}}.$
(d) Diode+$R$ (anode at $v_O$) in parallel with diode+$2R$ (cathode at $v_O$). Left diode conducts high, right diode conducts low; charge balance $\dfrac{v_{O,\text{hi}}-0.7}{R}+\dfrac{v_{O,\text{lo}}+0.7}{2R}=0$ again yields $V_C=3.1$ V and $\boxed{v_O:\ +6.9\ \text{V}/-13.1\ \text{V}}.$
(e) Single diode (anode at $v_O$) to a $-5$ V rail. The diode conducts once $v_O$ exceeds $-5+0.7=-4.3$ V, pinning the positive peak there (again no discharge path when blocked): $V_C=10-(-4.3)=14.3$ V and $\boxed{v_O:\ -4.3\ \text{V (high)},\ -24.3\ \text{V (low)}}$ (clamp shifted to $-5$ V).

(a) Negative clamp: top pinned at $+0.7$ V.

(b) Symmetric anti-parallel diodes: no DC shift, output $\approx$ input.

(d) Partial clamp, $V_C=3.1$ V (same levels as (c)).

(e) Clamp referenced to $-5$ V: top at $-4.3$ V.

Question 5 — steady-state output levels
Circuit	(a)	(b)	(c)	(d)	(e)
High level	+0.7 V	+10 V	+6.9 V	+6.9 V	−4.3 V
Low level	−19.3 V	−10 V	−13.1 V	−13.1 V	−24.3 V

Check — flat tops. With $RC\gg T$ the capacitor voltage is nearly constant, so each level is essentially flat (negligible droop). In (a) and (e) the diode has no discharge path when it blocks, giving an ideal clamp; in (b), (c) and (d) a small triangular ripple of order $v_{pk}\,T/(RC)$ rides on the levels.

Topic. Diode clampers / DC restorers driven by a square wave.

Key relations. $v_O=v_I-V_C$; steady state $\Rightarrow$ average capacitor current $=0$ over a period; a hard one-sided clamp pins a peak at $\pm V_\gamma$ (or at $V_{ref}\pm V_\gamma$).

Why this works. The large series capacitor cannot pass DC, so it charges to whatever constant $V_C$ makes the diode network’s current balance over a cycle. A single diode with no bleed path clamps a peak exactly to its threshold; adding resistive paths lets some charge leak each cycle, so the clamp is only partial and the DC shift is smaller.

Common pitfall. Treating a diode+resistor branch as a hard voltage clamp — the series $R$ (and the coupling $C$) mean the node voltage is not pinned to $0.7$ V; only charge balance gives the correct levels. Also, symmetric networks (b) give no DC restoration.

Source. Boylestad & Nashelsky, Electronic Devices and Circuit Theory (clampers); Sedra & Smith, Ch. 4.

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