22-Elec-A5 Electronics · May 2017

Question 4 of 5: Two-Stage BJT DC Bias (NPN + PNP)

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

National Exams — May 2017 · 16-Elec-A5, Electronics. Closed-book, 3 hours; answer all FIVE questions (20 marks each). Op-amps ideal, supplies ±15 V (Note 7).

Reference texts (22-Elec-A5 Electronics):

A. S. Sedra & K. C. Smith, Microelectronic Circuits, 7th/8th ed. — Ch. 4 (diodes, clippers & clampers), Ch. 5–7 (MOSFET/BJT biasing & small-signal amplifiers), Ch. 2 (op-amp circuits).
R. C. Jaeger & T. N. Blalock, Microelectronic Circuit Design, 5th ed. — single-stage amplifier design and DC bias.
Boylestad & Nashelsky, Electronic Devices and Circuit Theory — diode wave-shaping (clampers/DC restorers).

Check — drawing readings. Two readings of the printed schematics drive the answers: (Q1) the MOSFET source resistor $R_S$ has no bypass capacitor — the stage is a common-source amplifier with source degeneration. (Q4) the second transistor $Q_2$ is a PNP (emitter tied through $R_{E2}$ to $V_{CC}$, collector through $R_{C2}$ to ground), not an NPN.

Question 4: Two-Stage BJT DC Bias (NPN + PNP) (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Stage 1 is an NPN $Q_1$ with a base divider $R_{B1}/R_{B2}$, collector load $R_{C1}$ to $V_{CC}$ and emitter resistor $R_{E1}$ to ground. Stage 2 is a PNP $Q_2$ whose base is $V_{C1}$, emitter tied through $R_{E2}$ to $V_{CC}$ and collector through $R_{C2}$ to ground. Take $V_{BE}=V_{EB}=0.7$ V.

Given data
$R_{B1}$	100 kΩ	$R_{B2}$	50 kΩ	$R_{C1}$	5 kΩ
$R_{E1}$	3 kΩ	$R_{C2}$	2.7 kΩ	$R_{E2}$	2 kΩ
$\beta$	100	$V_{BE}$	0.7 V	$V_{CC}$	15 V (assumed)

Find. the ten DC quantities $V_{B1},V_{E1},V_{C1},V_{B2},V_{E2},V_{C2},I_{C1},I_{B1},I_{C2},I_{B2}$.

[Figure not reproduced: circuit. See the official exam paper or the cited reference text.]

Figure 4.1 — Stage 1 NPN $Q_1$ (left); stage 2 PNP $Q_2$ (right, emitter up to $V_{CC}$ through $R_{E2}$). The collector of $Q_1$ is the base of $Q_2$.

Approach. Solve $Q_1$ from a Thévenin base bias with emitter degeneration; then solve $Q_2$ (PNP), remembering that its base current loads the $V_{C1}$ node through $R_{C1}$, so $V_{C1}$ and $I_{B2}$ are found together.

Thévenin base of $Q_1$. $V_{TH}=V_{CC}\dfrac{R_{B2}}{R_{B1}+R_{B2}}=15\cdot\dfrac{50}{150}=5\ \text{V},\quad R_{TH}=R_{B1}\Vert R_{B2}=33.3\ \text{k}\Omega.$
Base current and $I_{C1}$. $I_{B1}=\dfrac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_{E1}}=\dfrac{5-0.7}{33.3\ \text{k}+101(3\ \text{k})}=12.8\ \mu\text{A};\ \ I_{C1}=\beta I_{B1}=1.28\ \text{mA}.$
$Q_1$ node voltages. $V_{E1}=(\beta+1)I_{B1}R_{E1}=3.87\ \text{V},\quad V_{B1}=V_{E1}+0.7=4.57\ \text{V}.$
Collector node $V_{C1}=V_{B2}$ with PNP loading. The PNP emitter current is $I_{E2}=\dfrac{V_{CC}-(V_{C1}+0.7)}{R_{E2}}$ and its base draws $I_{B2}=I_{E2}/(\beta+1)$ out of the node. KCL at the collector node, $\dfrac{V_{CC}-V_{C1}}{R_{C1}}+I_{B2}=I_{C1}$, solves to $\boxed{V_{C1}=8.75\ \text{V}}$ (the bare $V_{CC}-I_{C1}R_{C1}=8.61$ V shifts up by $I_{B2}R_{C1}\approx0.14$ V).
PNP currents. $I_{E2}=\dfrac{15-8.75-0.7}{2\ \text{k}}=2.78\ \text{mA},\ \ I_{B2}=27.5\ \mu\text{A},\ \ I_{C2}=\beta I_{B2}=2.75\ \text{mA}.$
Remaining $Q_2$ voltages. $V_{B2}=V_{C1}=8.75\ \text{V},\ \ V_{E2}=V_{C1}+0.7=9.45\ \text{V},\ \ V_{C2}=I_{C2}R_{C2}=2.75\ \text{mA}\times2.7\ \text{k}=7.43\ \text{V}.$
Region check. $Q_1$: $V_{C1}=8.75\gt V_{B1}=4.57$ (collector junction reverse) → active. $Q_2$ (PNP): $V_{E2}=9.45\gt V_{B2}=8.75\gt V_{C2}=7.43$ → active. Both assumptions hold.

Question 4 — DC operating point ($V_{CC}=15$ V)
$V_{B1}$	$V_{E1}$	$V_{C1}$	$V_{B2}$	$V_{E2}$	$V_{C2}$
4.57 V	3.87 V	8.75 V	8.75 V	9.45 V	7.43 V
$I_{C1}$	$I_{B1}$	$I_{C2}$	$I_{B2}$
1.28 mA	12.8 µA	2.75 mA	27.5 µA

Check — supply and device type. The exam does not print a numeric $V_{CC}$; $V_{CC}=15$ V is assumed to match the ±15 V supply convention of Note 7 (state-your-assumptions, Note 1). All voltages scale with $V_{CC}$; the method is unchanged for any other rail. $Q_2$ is read from the drawing as a PNP (emitter arrow into the base, emitter toward $V_{CC}$) — treating it as an NPN would put it in reverse/saturation and give nonsense.

Topic. DC bias of a directly-coupled two-stage amplifier mixing an NPN and a PNP stage.

Key relations. $I_B=\dfrac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E}$; $I_C=\beta I_B$; PNP active needs $V_E\gt V_B\gt V_C$; node KCL couples the stages.

Why this works. Emitter degeneration ($R_{E1}$) sets $I_{C1}$ almost independently of $\beta$. The collector of $Q_1$ is the base of the PNP $Q_2$; because $Q_2$’s base current also flows in $R_{C1}$, the coupling node $V_{C1}$ must be found from a single KCL rather than from $V_{CC}-I_{C1}R_{C1}$ alone. The PNP then works “upside down” relative to the NPN — current flows out of its collector down through $R_{C2}$ to ground.

Common pitfall. Mis-reading $Q_2$ as an NPN (its emitter is at the top toward $V_{CC}$), and ignoring $I_{B2}$’s loading of the $V_{C1}$ node.

Source. Sedra & Smith, Microelectronic Circuits, Ch. 6–7 (BJT biasing, NPN and PNP DC analysis).

← Question 3 Next: Question 5 →