Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Paper format. National Exams, December 2018 — 16-Elec-B5 Advanced Electronics. Three hours; CLOSED BOOK, an approved Casio or Sharp calculator permitted. Five questions, all to be answered, 20 marks each. Op-amps are ideal and supplies are ±15 V unless a question says otherwise; in schematics ground and chassis are common.
Reference texts. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. (the paper cites it by name for Question 3) — Ch. 8 differential and multistage amplifiers, Ch. 10 output stages and power amplifiers, Ch. 11 frequency response and compensation, Ch. 12 feedback, Ch. 17 tuned amplifiers. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., Ch. 4 (differential amplifiers) and Ch. 10 (stability and frequency compensation). P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Ch. 4 (current mirrors) and Ch. 9 (frequency response of feedback amplifiers).
Check: figure readings taken from the printed schematics. Three of the five figures need careful reading, and two of them contradict a plain reading of the accompanying prose. In Question 1 the input pair M1/M2 is a p-channel pair whose common source node is fed by M5, with M3/M4 as n-channel current-source loads — M6 and M7 are the two diode-connected devices of the reference string, not signal-path loads. In Question 4 the input vIN drives the source of M1 and the gate is tied to the R1/R2 tap, so the forward path is a common-gate stage; were the input on the gate, part (a)'s RIN would be infinite and its 8 marks unearnable. Both readings are stated where they are used.
